SLVSES8A
October 2020 – December 2020
LM5127-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Device Enable (EN, VCC_HOLD)
8.3.2
Dual Input VCC Regulator (BIAS, VCCX, VCC)
8.3.3
Dual Input VDD Switch (VDD, VDDX)
8.3.4
Device Configuration and Light Load Switching Mode Selection (CFG/MODE)
8.3.5
Fixed or Adjustable Output Regulation Target (VOUT, FB)
8.3.6
Overvoltage Protection (VOUT, FB)
8.3.7
Power Good Indicator (PGOOD)
8.3.8
Programmable Switching Frequency (RT)
8.3.9
External Clock Synchronization (SYNC)
8.3.10
Programmable Spread Spectrum (DITHER)
8.3.11
Programmable Soft Start (SS)
8.3.12
Fast Re-start using VCC_HOLD (VCC_HOLD)
8.3.13
Transconductance Error Amplifier and PWM (COMP)
8.3.14
Current Sensing and Slope Compensation (CSA, CSB)
8.3.15
Constant Peak Current Limit (CSA, CSB)
8.3.16
Maximum Duty Cycle and Minimum Controllable On-time Limits (Boost)
8.3.17
Bypass Mode (Boost)
8.3.18
Minimum Controllable On-time and Minimum Controllable Off-time Limits (Buck)
8.3.19
Low Dropout Mode for Extended Minimum Input Voltage (Buck)
8.3.20
Programmable Hiccup Mode Overload Protection (RES)
8.3.21
MOSFET Drivers and Hiccup Mode Fault Protection (LO, HO, HB)
8.3.22
Battery Monitor (BMOUT, BMIN_FIX, BMIN_PRG)
8.3.23
Dual-phase Interleaved Configuration for High Current Supply (CFG)
8.3.24
Thermal Shutdown Protection
8.3.25
External VCCX Supply Reduces Power Dissipation
8.4
Device Functional Modes
8.4.1
Device Status
8.4.1.1
Shutdown Mode
8.4.1.2
Configuration Mode
8.4.1.3
Active Mode
8.4.1.4
Sleep Mode
8.4.1.5
Deep Sleep Mode
8.4.1.5.1
Cutting Leakage Path in Deep Sleep Mode (DIS, SLEEP1, SENSE1)
8.4.1.6
VCC HOLD Mode
8.4.2
Light Load Switching Mode
8.4.2.1
Forced PWM (FPWM) Operation
8.4.2.2
Diode Emulation (DE) Operation (Connect RSS at SS)
8.4.2.3
Forced Diode Emulation Operation in FPWM Mode
8.4.2.4
Skip Mode Operation
8.4.3
LM5127 Cheat Sheet
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Recommended Power Tree Architecture
9.2.2.2
Application Ideas
9.2.3
Application Curves
9.3
System Examples
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.1.2
Development Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGZ|48
MPQF123F
Thermal pad, mechanical data (Package|Pins)
RGZ|48
QFND585
Orderable Information
slvses8a_oa
slvses8a_pm
1
Features
AEC-Q100 qualified for automotive applications
Temperature grade 1: –40°C to +125°C, T
A
Functional Safety-Capable
Documentation available to aid functional safety system design
Suited for various architectures and scalable
Triple-output synchronous controllers
Flexible topology
CH1: boost / buck topology
CH2, CH3: two single phase bucks / dual-phase interleaved buck topology
Enable pin and PGOOD indicator per channel
Optional low I
Q
battery monitor
Wide operating range for automotive applications
3.8-V to 42-V input operating range
Minimum boost input 0.8 V when BIAS ≥ 3.8 V
Boost output: adjustable up to 42 V
Buck output: fixed 3.3 V, 5 V, or adj. 0.8 - 42 V
Bypass operation when V
SUPPLY
>V
LOAD
(boost)
LDO operation when V
SUPPLY
≈ V
LOAD
(buck)
Minimized battery drain
Shutdown current ≤ 2.8 μA
Automatic transition to low-I
Q
sleep mode
Battery drain in sleep
I
Q
≤ 14 μA when 3.3-V buck on
I
Q
≤ 22 μA when 3.3-V and 5-V bucks on
I
Q
≤ 32 μA when 3.3-V, 5-V bucks on and boost in bypass
High efficiency using strong 5-V drivers
Dual input VCC and VDD regulators
Small and cost-effective solution
Maximum switching frequency 2.2 MHz
Internal boot diode (boost)
Constant peak current limit
Supports DCR inductor current sensing
QFN-48 with wettable flanks
Avoid AM band interference and crosstalk
Optional clock synchronization
Switching frequency from 100 kHz to 2.2 MHz
Selectable switching mode (FPWM, diode emulation, and skip mode)
EMI mitigation
Optional programmable spread spectrum
Programmability and flexibility
Programmable wake-up and sleep threshold
Dynamic switching frequency programming
Adjustable soft start time
Adjustable output using 0.8 V ±1% reference
Adaptive dead-time control
Integrated protection features
Overcurrent protection
Cycle-by-cycle peak current limit
Optional hiccup mode protection (buck)
Optional latch-off mode protection (buck)
Overvoltage protection
HB-SW short protection (boost)
Thermal shutdown