SLVSFF2A February   2022  – April 2022 LM5152-Q1 , LM51521-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Enable/Disable (EN, VH Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 9.3.4  Line Undervoltage Lockout (UVLO Pin)
      5. 9.3.5  Fast Restart Using VCC HOLD (VH Pin)
      6. 9.3.6  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      7. 9.3.7  Overvoltage Protection (VOUT Pin)
      8. 9.3.8  Boost Status Indicator (STATUS Pin)
      9. 9.3.9  Dynamically Programmable Switching Frequency (RT)
      10. 9.3.10 External Clock Synchronization (SYNC Pin)
      11. 9.3.11 Programmable Spread Spectrum (DITHER Pin)
      12. 9.3.12 Programmable Soft Start (SS Pin)
      13. 9.3.13 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      14. 9.3.14 Current Sensing and Slope Compensation (CSP, CSN Pin)
      15. 9.3.15 Constant Peak Current Limit (CSP, CSN Pin)
      16. 9.3.16 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      17. 9.3.17 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      18. 9.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 9.3.19 Thermal Shutdown Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Status
        1. 9.4.1.1 Shutdown Mode
        2. 9.4.1.2 Configuration Mode
        3. 9.4.1.3 Active Mode
        4. 9.4.1.4 Sleep Mode
        5. 9.4.1.5 Deep Sleep Mode
      2. 9.4.2 Light Load Switching Mode
        1. 9.4.2.1 Forced PWM (FPWM) Mode
        2. 9.4.2.2 Diode Emulation (DE) Mode
        3. 9.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 9.4.2.4 Skip Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application Ideas
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.4 Line Undervoltage Lockout (UVLO Pin)

When UVLO is greater than the UVLO threshold (VUVLO), the device enters active mode if the device configuration is finished. UVLO hysteresis is accomplished with an internal 25-mV voltage hysteresis (VUVLO-HYS) at the UVLO pin, and an additional 10-μA current sink (IUVLO-HYS) that is switched on or off. When the UVLO pin voltage exceeds VUVLO, the current sink is disabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below VUVLO or during the device configuration time, the current sink is enabled, causing the voltage at the UVLO pin to fall quickly.

The external UVLO resistor voltage divider (RUVLOT, RUVLOB) must be designed so that the voltage at the UVLO pin is greater than VUVLO when VSUPPLY is in the desired operating range. The values of RUVLOT and RUVLOB can be calculated as follows.

Equation 2. R U V L O T = V S U P P L Y _ O N - V U V L O _ R I S I N G V U V L O _ F A L L I N G × V S U P P L Y _ O F F I U V L O _ H Y S
Equation 3. R U V L O B = V U V L O _ F A L L I N G × R U V L O T V S U P P L Y _ O F F - V U V L O _ F A L L I N G

A UVLO capacitor (CUVLO) is required in case VSUPPLY drops below VSUPPLY-OFF momentarily during the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when IUVLO-HYS is disabled.

The UVLO pin can be connected to the BIAS pin if not used. Drive the UVLO pin through a minimum of a 5-kΩ resistor if the BIAS pin voltage is less than the UVLO pin voltage in any conditions.