SLVSFF2A February   2022  – April 2022 LM5152-Q1 , LM51521-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Enable/Disable (EN, VH Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 9.3.4  Line Undervoltage Lockout (UVLO Pin)
      5. 9.3.5  Fast Restart Using VCC HOLD (VH Pin)
      6. 9.3.6  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      7. 9.3.7  Overvoltage Protection (VOUT Pin)
      8. 9.3.8  Boost Status Indicator (STATUS Pin)
      9. 9.3.9  Dynamically Programmable Switching Frequency (RT)
      10. 9.3.10 External Clock Synchronization (SYNC Pin)
      11. 9.3.11 Programmable Spread Spectrum (DITHER Pin)
      12. 9.3.12 Programmable Soft Start (SS Pin)
      13. 9.3.13 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      14. 9.3.14 Current Sensing and Slope Compensation (CSP, CSN Pin)
      15. 9.3.15 Constant Peak Current Limit (CSP, CSN Pin)
      16. 9.3.16 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      17. 9.3.17 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      18. 9.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      19. 9.3.19 Thermal Shutdown Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Status
        1. 9.4.1.1 Shutdown Mode
        2. 9.4.1.2 Configuration Mode
        3. 9.4.1.3 Active Mode
        4. 9.4.1.4 Sleep Mode
        5. 9.4.1.5 Deep Sleep Mode
      2. 9.4.2 Light Load Switching Mode
        1. 9.4.2.1 Forced PWM (FPWM) Mode
        2. 9.4.2.2 Diode Emulation (DE) Mode
        3. 9.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 9.4.2.4 Skip Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application Ideas
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.6 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)

The VOUT regulation target (VOUT-REG) is adjustable by programming the TRK pin voltage, which is the reference of the internal error amplifier. The accuracy of VOUT-REG is given when the TRK voltage is between 0.25 V and 1.0 V. The high impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by connecting to a resistor voltage divider (RVREFT, RVREFB) between VREF and AGND.

The device provides a 1-V voltage reference (VREF), which can be used to program the TRK pin voltage through a resistor voltage divider. It is not recommended to use VREF as a reference voltage of an external circuit because the device periodically disables VREF in sleep or deep sleep mode. For stability reasons, the VREF capacitor (CVREF) should be between 330 pF and 1 nF. 470 pF is recommended.

When RVREFT and RVREFB are used to program the TRK pin voltage, VOUT-REG can be calculated as follows.

Equation 4. V O U T _ R E G = 20 × R V R E F B R V R E F B + R V R E F T

The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage comparator is not triggered during the transient operation. An RC filter must be used at the TRK pin to slow down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When a trapezoidal or sinusoidal input is applied, the slew rate or the frequency of the command signal must be limited.

GUID-20200809-CA0I-PSWK-CSVF-6PTHCHZMKKPH-low.gif Figure 9-6 TRK Control (a) Using VREF (b) by External Step Input

VOUT-REG tracks the TRK pin voltage in all operation modes (FPWM, skip or diode mode) with a maximum of a 20-ms delay during deep sleep mode to save power. Take extra care when programming TRK if VSUPPLY is greater than VOUT-REG in any conditions. The device enters active mode with a 5-μs delay if VLOAD falls below VOUT-REG in deep sleep mode, but the device enters active mode with maximum of a 20-ms delay if VOUT-REG is increased by TRK above VLOAD in deep sleep mode.