SNVSBU4E June   2022  – August 2024 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Gate Driver Rise Time and Fall Time
    2. 6.2 Gate Driver Dead (Transition) Time
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On Reset (POR System)
      2. 7.3.2  Buck-Boost Control Scheme
        1. 7.3.2.1 Boost Mode
        2. 7.3.2.2 Buck Mode
        3. 7.3.2.3 Buck-Boost Mode
      3. 7.3.3  Power Save Mode
      4. 7.3.4  Supply Voltage Selection – VMAX Switch
      5. 7.3.5  Enable and Undervoltage Lockout
      6. 7.3.6  Oscillator Frequency Selection
      7. 7.3.7  Frequency Synchronization
      8. 7.3.8  Voltage Regulation Loop
      9. 7.3.9  Output Voltage Tracking
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Configurable Soft Start
      12. 7.3.12 Peak Current Sensor
      13. 7.3.13 Current Monitoring and Current Limit Control Loop
      14. 7.3.14 Short Circuit - Hiccup Protection
      15. 7.3.15 nFLT Pin and Protections
      16. 7.3.16 Device Configuration Pin
      17. 7.3.17 Dual Random Spread Spectrum – DRSS
      18. 7.3.18 Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  Feedback Divider
        4. 8.2.2.4  Inductor and Current Sense Resistor Selection
        5. 8.2.2.5  Slope Compensation
        6. 8.2.2.6  Output Capacitor
        7. 8.2.2.7  Input Capacitor
        8. 8.2.2.8  UVLO Divider
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 MOSFETs QH1 and QL1
        11. 8.2.2.11 MOSFETs QH2 and QL2
        12. 8.2.2.12 Frequency Compensation
        13. 8.2.2.13 External Component Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Bi-Directional Power Backup
      2. 8.3.2 Parallel (Multiphase) Operation
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Driver Layout
      3. 10.1.3 Controller Layout
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.4 Inductor and Current Sense Resistor Selection

For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple, ΔIL, to approximately 20% of the maximum inductor current at the minimum input voltage. The target inductance for boost mode is:

Equation 19. LBOOST= VIN(MIN)2×VOUT-VIN(MIN)0.2× IOUTMAX× fSW× VOUT2= 2.21μH

For this application, an inductor with 1.8 μH was selected.

When selecting the current sense resistor it needs to be ensured the peak inductor current will not hit the over current limit at maximum output current. For that the peak inductor current needs to be calculated with the sum of the average and ripple current through the inductor.

The maximum peak to peak inductor current occurs at minimum input voltage and is given by:

Equation 20. IL(PEAK,PEAK)=1-VINMINVOUT×VIN(MIN)L×fSW=5.23 A
The average input current at the maximum output current with an estimated efficiency of 95% is calculated by:
Equation 21. IIN,AVG(MAX)=VOUT×IOUTMAX95%×VINMIN=22.5 A
For the current sense Resistor a margin of 20% is considered to have enough headroom for the dymamic responses, e.g. load step regulation. To ensure the maximum output current can be delivered the mimium level of the peak current limit threshold is used.
Equation 22. RCS=38.5 mVIIN,AVGMAX+12IIN,AVGMax×1.2=1.28 mΩ

The standard value of RCS = 1 mΩ with 3 times 3 mΩ is selected. With the 3 resistors in parallel it also reduces the parasitic inductance.

The maximum power dissipation in RCS happens at VIN(MAX):

Equation 23. PRCS(MAX)= 58.5 mVRCS2× RCS× 1-VOUTVINMAX= 1.90W

Therefore, for the 3 resistors in parallel a sense resistor with 1-W power rating is sufficient for this application.

For some application circuits, it can be required to add a filter network to attenuate noise in the CS and CSG sense lines. The filter resistance must not exceed 100 Ω.