SNVSBU4E June   2022  – August 2024 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Gate Driver Rise Time and Fall Time
    2. 6.2 Gate Driver Dead (Transition) Time
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On Reset (POR System)
      2. 7.3.2  Buck-Boost Control Scheme
        1. 7.3.2.1 Boost Mode
        2. 7.3.2.2 Buck Mode
        3. 7.3.2.3 Buck-Boost Mode
      3. 7.3.3  Power Save Mode
      4. 7.3.4  Supply Voltage Selection – VMAX Switch
      5. 7.3.5  Enable and Undervoltage Lockout
      6. 7.3.6  Oscillator Frequency Selection
      7. 7.3.7  Frequency Synchronization
      8. 7.3.8  Voltage Regulation Loop
      9. 7.3.9  Output Voltage Tracking
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Configurable Soft Start
      12. 7.3.12 Peak Current Sensor
      13. 7.3.13 Current Monitoring and Current Limit Control Loop
      14. 7.3.14 Short Circuit - Hiccup Protection
      15. 7.3.15 nFLT Pin and Protections
      16. 7.3.16 Device Configuration Pin
      17. 7.3.17 Dual Random Spread Spectrum – DRSS
      18. 7.3.18 Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  Feedback Divider
        4. 8.2.2.4  Inductor and Current Sense Resistor Selection
        5. 8.2.2.5  Slope Compensation
        6. 8.2.2.6  Output Capacitor
        7. 8.2.2.7  Input Capacitor
        8. 8.2.2.8  UVLO Divider
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 MOSFETs QH1 and QL1
        11. 8.2.2.11 MOSFETs QH2 and QL2
        12. 8.2.2.12 Frequency Compensation
        13. 8.2.2.13 External Component Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Bi-Directional Power Backup
      2. 8.3.2 Parallel (Multiphase) Operation
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage Layout
      2. 10.1.2 Gate Driver Layout
      3. 10.1.3 Controller Layout
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 Voltage Regulation Loop

The LM5177 features an internal error amplifier (EA) to regulate the output voltage. The output voltage gets sensed on the FB pin through external resistors, which determine the target or nominal output voltage. The reference for the EA builds the soft-start and analog output voltage tracking pin (SS/ATRK). The COMP pin is the output of the internal gm-stage and gets connected to the external compensation network. The voltage over the compensation network is the nominal value for the inner peak current control loop of the device.


LM5177 Functional Block Diagram of the Voltage and Peak Current Control Loop

Figure 7-13 Functional Block Diagram of the Voltage and Peak Current Control Loop

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Use the following equations to calculate the external components:

External Feedback:

Equation 3. R(COMP)= 2π ×f(BW) gm(ea) ×R(FB,bot) + R(FB,top)R(FB,bot)×10 ×R(CS)×CO1-Dmax
Equation 4. C(COMP)= 1 2π× f(CZ)×R(COMP)
Equation 5. C(PCOMP)= 1 2π×10× f(BW)×R(COMP)

For most applications, TI recommends the following guidelines for bandwidth selection of the compensation.

The hard limit of the bandwidth (f(BW)) is the right half plane zero of the boost operation:

Equation 6. fRHPZ=12π×V(VOUT)×(1-Dmax)2Io,max×L

The maximum recommended bandwidth must be within the following boundaries:

Equation 7. f(BW)<13×fRHPZ
Equation 8. f(BW)<110×(1-Dmax)×f(SW)

The compensation zero (fCZ) must be placed in relation to the dominating pole of the boost.

Equation 9. fCZ=1.5×fpole,boost
Equation 10. fpole,boost=12π×2×Io,maxV(VOUT)×Co

Due to the precise implementation of the error amplifier, the voltage on the LM5177 COMP pin is accurately reflecting the nominal peak current value of the inductor. Figure 7-14 shows the control V/I-characteristics of the error amplifier in FPWM mode. Use this as a guidance for applicative designs where you need to manipulate the inner current loop regulation.


LM5177 Control Function for the Peak Current Sense Voltage Versus VCOMP

Figure 7-14 Control Function for the Peak Current Sense Voltage Versus VCOMP