SNVSC22B October   2023  – June 2024 LM51772

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck-Boost Control Scheme
        1. 7.3.1.1 Buck Mode
        2. 7.3.1.2 Boost Mode
        3. 7.3.1.3 Buck-Boost Mode
      2. 7.3.2  Power Save Mode
      3. 7.3.3  Programmable Conduction Mode PCM
      4. 7.3.4  Reference System
        1. 7.3.4.1 VIO LDO and nRST-PIN
      5. 7.3.5  Supply Voltage Selection – VSMART Switch and Selection Logic
      6. 7.3.6  Enable and Undervoltage Lockout
        1. 7.3.6.1 UVLO
        2. 7.3.6.2 VDET Comparator
      7. 7.3.7  Internal VCC Regulators
        1. 7.3.7.1 VCC1 Regulator
        2. 7.3.7.2 VCC2 Regulator
      8. 7.3.8  Error Amplifier and Control
        1. 7.3.8.1 Output Voltage Regulation
        2. 7.3.8.2 Output Voltage Feedback
        3. 7.3.8.3 Voltage Regulation Loop
        4. 7.3.8.4 Dynamic Voltage Scaling
      9. 7.3.9  Output Voltage Discharge
      10. 7.3.10 Peak Current Sensor
      11. 7.3.11 Short Circuit - Hiccup Protection
      12. 7.3.12 Current Monitor/Limiter
        1. 7.3.12.1 Overview
        2. 7.3.12.2 Output Current Limitation
        3. 7.3.12.3 Output Current Monitor
      13. 7.3.13 Oscillator Frequency Selection
      14. 7.3.14 Frequency Synchronization
      15. 7.3.15 Output Voltage Tracking
        1. 7.3.15.1 Analog Voltage Tracking
        2. 7.3.15.2 Digital Voltage Tracking
      16. 7.3.16 Slope Compensation
      17. 7.3.17 Configurable Soft Start
      18. 7.3.18 Drive Pin
      19. 7.3.19 Dual Random Spread Spectrum – DRSS
      20. 7.3.20 Gate Driver
      21. 7.3.21 Cable Drop Compensation (CDC)
      22. 7.3.22 CFG-pin and R2D Interface
      23. 7.3.23 Advanced Monitoring Features
        1. 7.3.23.1  Overview
        2. 7.3.23.2  BUSY
        3. 7.3.23.3  OFF
        4. 7.3.23.4  VOUT
        5. 7.3.23.5  IOUT
        6. 7.3.23.6  INPUT
        7. 7.3.23.7  TEMPERATURE
        8. 7.3.23.8  CML
        9. 7.3.23.9  OTHER
        10. 7.3.23.10 ILIM_OP
        11. 7.3.23.11 nFLT/nINT Pin Output
        12. 7.3.23.12 Status Byte
      24. 7.3.24 Protection Features
        1. 7.3.24.1  Thermal Shutdown (TSD)
        2. 7.3.24.2  Over Current Protection
        3. 7.3.24.3  Output Over Voltage Protection 1 (OVP1)
        4. 7.3.24.4  Output Over Voltage Protection 2 (OVP2)
        5. 7.3.24.5  Input Voltage Protection (IVP)
        6. 7.3.24.6  Input Voltage Regulation (IVR)
        7. 7.3.24.7  Power Good
        8. 7.3.24.8  Boot-Strap Under Voltage Protection
        9. 7.3.24.9  Boot-strap Over Voltage Clamp
        10. 7.3.24.10 CRC - CHECK
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overview
      2. 7.4.2 Logic State Description
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. 8 LM51772 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Slope Compensation
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Loop Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate Driver Layout
        3. 9.4.1.3 Controller Layout
      2. 9.4.2 Layout Example
    5. 9.5 USB-PD Source with Power Path
    6. 9.6 Parallel (Multiphase) Operation
    7. 9.7 Constant Current LED Driver
    8. 9.8 Wireless Charging Supply
    9. 9.9 Bi-Directional Power Backup
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125°C. Unless otherwise stated, V(BIAS) =12 V
PARAMETER MIN TYP MAX UNIT
SUPPLY CURRENT
Shutdown current into VIN V(VIN) = 48 V,  V(BIAS) = 0 V V(EN) = 0 V TJ = 25°C 3.6 4.7 µA
TJ = –40°C to 125°C 3.6 7.5 µA
Shutdown current into BIAS  V(VIN) = 0 V,  V(EN) = 0 V TJ = 25°C 2.8 4.7 µA
TJ = –40°C to 125°C 2.8 6 µA
Stand-by  current into VIN V(VIN) = 12 V,  V(BIAS) = 0 V;  V(nRST) = High TJ = 25°C 55 75 µA
TJ = –40°C to 125°C 55 100 µA
Quiescent current into BIAS  V(EN) = 3.3 V, V(FB) > 1 V, uSleep enabled, ILIMCOMP = V(VCC2) , EN_VCC1 = 0b0  TJ = 25°C 65 75 µA
TJ = –40°C to 125°C 65 100 µA
VCC1 REGULATOR
VCC1 regulation VI = 12.0 V ,I(VCC1) = 1 mA 4.95 5 5.05 V
VCC1 drop-out voltage  I(VCC1) = 34 mA VI = 5 V 0.6 1.4 V
VI = 4.5 V 0.6 1.5 V
VCC1 sourcing current limit VCC1=GND VI = 12V 34 70 mA
VCC2 REGULATOR
VCC2 regulation VBIAS =12.0 V ,I(VCC2) = 20 mA 4.85 5 5.1 V
VCC2 drop-out voltage  I(VCC2) = 45 mA  VI = 4 V 130 300 mV
VI = 3.5 V 190 400 mV
VCC2 sourcing current limit V(VCC2)  ≥ 3 V VI = 6V, VBIAS = 12V 200 260 450 mA
VT+(VCC2) Positive going threshold  V(VCC2) rising 3.3 3.35 3.4 V
VT-(VCC2) Negative going threshold  V(VCC2) falling 3 3.05 3.1 V
VT+(Force,BIAS) Positive going threshold for Forced V(BIAS) FORCE_BIASPIN = 0b1 4.5 4.6 4.7 V
Vhyst(Force,BIAS) LDO switch-over hystereses for Forced V(BIAS) 230 275 mV
VT+(VCC2,SUP) Positive going treshold for LDO switch-over  FORCE_BIASPIN = 0b0 6.7 6.8 6.9 V
Vhyst(VCC2,SUP) LDO switch-over hysteresis   350 400 mV
VCC2 UVLO  rising detection delay time  V(VCC2) rising 100 µs
nRST
VT+(nRST) Enable positive-going threshold  nRST rising 1.4 V
VT-(nRST) Enable negative-going threshold  nRST falling 0.35 V
Vhyst(nRST) Enable threshold hysteresis 300 mV
EN/UVLO
VDET positive-going threshold  V(VIN) rising, VDET_RISE = 0x3 3.3 3.4 3.5 V
VDET negative-going threshold  V(VIN) falling, VDET_FALL = 0x0 2.6 2.7 2.799 V
VT+(UVLO) UVLO positive-going threshold  V(EN/UVLO) rising 1.23 1.25 1.27 V
VT-(UVLO) UVLO negative-going threshold  V(EN/UVLO) falling 1.18 1.2 1.22 V
Vhyst(UVLO) UVLO threshold hysteresis 38 50 62 mV
IUVLO UVLO hystereses sinking current V(EN/UVLO) < 1.26 V 4 5 6 µA
td(UVLO) UVLO  detection delay time  V(EN/UVLO) falling; 25.5 30 38.5 µs
VT+(POR) POR positive-going threshold  POR positive-going threshold  VIN rising or BIAS rising 1.75 V
VT-(POR) POR negative-going threshold  POR negative-going threshold  VIN falling or BIAS falling 1.7 V
SYNC
VT+(SYNC) Sync input positive going threshold 1.19 V
VT-(SYNC) Sync input negative going threshold 0.41 V
Sync activity detection frequency 99 kHz
td(Det,Sync) Sync activity detection frequency threshold refered to f(SYNC)  3 cycles
Sync PLL lock time refered to f(SYNC)  until f(SYNC) - 5% < f(sw) < f(SYNC) + 5% 10 cycles
SYNC high level output voltage drop EN_SYNC_OUT = 0b1
I(SYNC) = 2 mA, V(VCC2)  ≥ 3.5 V, 		 Referenced to  V(VCC2) 0.4 V
SYNC low level output voltage    0.3 V
SYNC output drive strength  EN_SYNC_OUT = 0b1
V(VCC2) = 5 V 		 sink –42 –31 –22 mA
source  22 34 42 mA
SOFT-START
I(SS) Soft-start current 9 10 11 uA

SS pull-down switch RDS(on)
 		 V(SS) = 1 V 21 40 Ω
td(DISCH;SS) SS Pin discharge time  Time from internal SS discharge until the soft-start current can charge the pin again 500 µs
td(EN_SS) SS Pin ramp start delay time Internal delay until soft-start current starts 2.5 4 µs
V(SS,clamp) Clamp Voltage for SS pin 4.1 V
VOUT TRACKING
VT+(DTRK) DTRK positive-going threshold  V(DTRK) rising 1.19 V
VT-(DTRK) DTRK negative-going threshold  V(DTRK) falling 0.41 V
DTRK activity dectection frequency DTRK activity detection frequency 148 kHz
td(DTRK) DTRK detection delay time  3 cycles
fc(LPF) Corner frequency of internal low pass 40 kHz
V(REF)voltage offset error  V(REF)voltage offset error  f(DTRK) = 500kHz, duty = 50%, V(REF) = 1V ±10 mV
PULSE WIDTH MODULATION
Switching frequency RRT = 14.20kΩ, 2000 2200 2400 kHz
RRT = 15.63kΩ, 1845 2000 2255 kHz
RRT = 316kΩ, 90 100 110 kHz
Minimum controllable on-time fPWM, RRT = 14 kΩ, positive inductor current Boost Mode 64 ns
Buck Mode  107 ns
Minimum controllable off-time Boost Mode 96 ns
Buck Mode  97 ns
RT regulation voltage 0.75 V
MODE SELECTION
VT+(MODE) Mode input positive going threshold 1.19 V
VT-(MODE) Mode input negative going threshold 0.41 V
CURRENT SENSE
Positive peak current  limit threshold  45 50 55 mV
Negative peak current limit threshold  –56 –50 –44 mV
AVERAGE CURRENT LIMIT
Current sense amplifier transconductance I2C interface disabled or SEL_ISET_PIN = 0b1; V(ISNSP) > 3.3V; EN_NEG_CL_LIMIT = 0 25 mV ≤ ΔV(ISNS) ≤ 50 mV 0.9 1 1.1 mS
Offset voltage VISNS > 4.8V TJ= 25℃ -1.5 0 1.5 mV
VISNS > 4.8V TJ=-40°C to 125°C -2.5 0 2.5 mV
Current sense amplifier output current  I2C interface disabled or SEL_ISET_PIN = 0b1; V(ISNSP) > 3.3V; EN_NEG_CL_LIMIT = 0 5 mV 2 5 8 µA
25 mV 21.5 25 28.5 µA
50 mV 45 50 55 µA
gm(ILIMCOMP) Current sense amplifier transconductance I2C interface enabled and  SEL_ISET_PIN = 0b0
VISNS > 4.8V;
N_NEG_CL_LIMIT = 0		 ΔV(ISNS) = 30mV and 50mV 450 500 550 µS
Current limit  R(ISNS) = 10mΩ±1%; ILIM_THRESHOLD = 0x64 4.75 5 5.25 A
ΔV(ISNSx) Current limit threshold voltage ILIM_THRESHOLD = 0x14 EN_NEG_CL_LIMIT = 0J=-10°C to 70°C; ISNSP/N ≥ 5 V;  8.6 10 11.4 mV
Current limit threshold voltage ILIM_THRESHOLD = 0x3C 28.8 30 31.2 mV
Current limit threshold voltage ILIM_THRESHOLD = 0x64 48 50 52 mV
ΔV(ISNSx) Current limit threshold voltage Current limit threshold voltage ILIM_THRESHOLD = 0xFF EN_NEG_CL_LIMIT = 0J=-10°C to 70°C; ISNSP/N ≥ 5 V;  67.2 70 72.8 mV
Typical current limit threshold voltage programming range 5 70 mV
Current limit threshold voltage step size from 5mV to 68.5 mV 0.5 mV
Minimum voltage to disable ILIM Referred to VCC2 75 %
V(SET) ISET regulation threshold voltage 0.95 1 1.05 V
ERROR AMPLIFIER
VREF FB reference Voltage 0.97 1 1.03 V
FB pin leakage current  V(FB) = 1 V 2 60 nA
Output voltage accuracy  V(FB)= VCC2; SEL_DIV20=0b1 Vo,nom = 5V 4.75 5 5.25 V
Vo,nom = 20V 19.6 20 20.4 V
Vo,nom = 48V 47.04 48 48.96 V
Transconductance 510 600 690 µS
COMP sourcing current 95 uA
COMP sinking current 120 uA
COMP clamp voltage V(FB) = 990 mV 1.2 1.25 1.3 V
COMP clamp voltage V(FB) = 1.01 V 0.225 0.25 0.275 V
VT+(SEL,iFB) Minimum voltage to select internal FB operation V(FB) rising 2.6 V
td(uSleep) delay time to wake-up from uSleep 7 µs
OVP
VT+(OVP) Over-voltage rising threshold FB rising reference to VREF 107 110 113 %
VT-(OVP) Over-voltage falling threshold FB falling reference to VREF 101 105 109 %
VT+(OVP2) Over-voltage rising threshold V(VOUT) rising  V_OVP2 = 0b111111 53.5 55 56.5 V
Over-voltage de-glitch time  9 10 12.5 µs
nFLT
nFLT pull-down switch RDSON 1mA sinking 85 140 Ω
Under-voltage positive going threshold FB rising (referece to VREF) 92 95 97 %
Under-voltage negative going threshold FB falling (referece to VREF) 87 90 93 %
nFLT off-state leakage V(nFLT)=12V 100 nA
td(nFLT-PIN) Deglitch filter 20 37 us
MOSFET DRIVER
tr  Rise time  LO1, LO2 CG = 3.3nF 10 ns
tr  Fall time  CG = 3.3nF 8 ns
tf Rise time  HO1, HO2 CG = 3.3nF 15 ns
tf Fall time  CG = 3.3nF 15 ns
tt Transition (Dead) time  CG = 3.3nF R(RT) =  316 kΩ (0.1 MHz), 
SEL_MIN_DEADTIME_GDRV = 0b01,
SEL_SCALE_DT = 0b1, EN_CONST_TDEAD = 0b0		 42 ns
tt Transition (Dead) time  CG = 3.3nF R(RT) =  14.2 kΩ (2.2 MHz),
SEL_MIN_DEADTIME_GDRV = 0b01,
SEL_SCALE_DT = 0b1, EN_CONST_TDEAD = 0b0		 19.5 ns
Gate driver high side on-resistance  LO1, LO2 I(test) = 500 mA 1.8 Ω
Gate driver high side on-resistance  HO1, HO2 1.5 Ω
Gate driver low side on-resistance  LO1, LO2 0.9 Ω
Gate driver low side on-resistance  HO1, HO2 0.8 Ω
VTH- (BOOT_UV) Negative going boot-strap UVLO threshold V(HBx) - V(SWx)  falling  2.5 2.7 3.1 V
VTH- (BOOT_UV) Boot-strap UVLO hysteresis 300 mV
VTH+ (BST_OV) Positive going boot-strap over-voltage threshold V(HBx) - V(SWx)  rising, I_HBx=10mA  5.1 5.5 5.9 V
VTH (GATEOUT) Gate driver output switching detection LO1,LO2 referenced to VCC  37 %
VTH (GATEOUT) Gate driver output switching detection HO2, HO2 referenced to V(HBx) - V(SWx) 37 %
THERMAL SHUTDOWN
TT+J   Thermal shutdown threshold   Thermal shutdown threshold TJ rising 164 °C
Thermal shutdown hysteresis Thermal shutdown hysteresis 15 °C
THERMAL WARNING
  Thermal warning threshold TJ rising THW_THRESHOLD=0b00 140 °C
Thermal warning typ. programming range 95 140 °C
Thermal warning accuracy  ±10 °C
R2D INTERFACE
Internal reference resistor 31.77 33 34.23 kΩ
RCFG External selection resistor resistance R2D setting #0 0 0.1 kΩ
R2D setting #1 0.49567 0.511 0.52633 kΩ
R2D setting #2 1.1155 1.15 1.1845 kΩ
R2D setting #3 1.8139 1.87 1.9261 kΩ
R2D setting #4 2.6578 2.74 2.8222 kΩ
R2D setting #5 3.7151 3.83 3.9449 kΩ
R2D setting #6 4.9567 5.11 5.2633 kΩ
R2D setting #7 6.2953 6.49 6.6847 kΩ
R2D setting #8 8.0025 8.25 8.4975 kΩ
R2D setting #9 10.185 10.5 10.815 kΩ
R2D setting #10 12.901 13.3 13.699 kΩ
R2D setting #11 15.714 16.2 16.686 kΩ
R2D setting #12 19.885 20.5 21.115 kΩ
R2D setting #13 24.153 24.9 25.647 kΩ
R2D setting #14 29.197 30.1 31.003 kΩ
R2D setting #15 35.405 36.5 37.595 kΩ
Protection/Monitoring
SCP Hiccup mode on time 0.85 1 1.15 ms
SCP Hiccup mode off time  20.4 24 27.6 ms
CABLE DROP COMPENSATION
VOUT increase for cable drop compensation with external feedback  R(FB,top) = 100kΩ; CDC_GAIN=0b01 V(CDC) = 0.2 V 0.08 0.1 0.12 V
V(CDC) = 1 V 0.45 0.5 0.55 V
VOUT increase for cable drop compensation with internal feedback  CDC_GAIN=0b01 V(CDC) = 0.2 V 0.075 0.1 0.125 V
V(CDC) = 1 V 0.45 0.5 0.55 V
gm(CDC) CDC current sense amplifier transconductance ΔV(IMON) = 50 mV and 30 mV V(ISNSP) > 3.3V; EN_NEG_CL_LIMIT = 0 450 500 550 uS
CDC current sense amplifier bandwidth 1 MHz
Output current CDC ΔV(IMON) = 50 mV;
EN_NEG_CL_LIMIT = 0		 23.3 25.0 26.8 µA
ΔV(IMON) =  25mV;
EN_NEG_CL_LIMIT = 0		 10.6 12.5 14.4 µA
ΔV(IMON) = 5 mV;
EN_NEG_CL_LIMIT = 0		 0.8 2.5 4.2 µA
DRIVE PIN
Pull down resistance  SEL_DRV_SUP = 0b00, 0b01, 0b10 470 1400 Ω
Pull up resistance  SEL_DRV_SUP = 0b01 or SEL_DRV_SUP = 0b10,   530 1500 Ω
Maximum output current  SEL_DRV_SUP = 0b00, 0b01, 0b10 sink 3 9 16 mA
Maximum output current  SEL_DRV_SUP = 0b01 or SEL_DRV_SUP = 0b10,   source 5 9 14 mA
Pull down resistance  SEL_DRV_SUP = 0b11   330 900 Ω
Pull up resistance  450 1200
Ω
Maximum output current  sink 5 9 14 mA
Maximum output current  source 5 8 13 mA
Charge pump switching frequency  SEL_DRV_SUP = 0b11   100 kHz
OUTPUT DISCHARGE
Output discharge current  VO_DISCH = 0b00 17.5 25 32.5 mA
VO_DISCH = 0b01  35 50 65 mA
VO_DISCH = 0b10 52.5 75 97.5 mA
VTH-(DISCH) Discharge done threshold  0.4 0.5 0.6 V
SPREAD SPECTRUM
Switching frequency modulation range upper limit 7.8 %
Switching frequency modulation range lower limit –7.8 %