SNVSCE8 July   2024 LM5190-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PGOOD)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Low Dropout Mode
      7. 6.3.7  Dual Random Spread Spectrum (DRSS)
      8. 6.3.8  Soft Start
      9. 6.3.9  Output Voltage Setpoint (FB)
      10. 6.3.10 Minimum Controllable On Time
      11. 6.3.11 Inductor Current Sense (ISNS+, VOUT)
      12. 6.3.12 Voltage Loop Error Amplifier
      13. 6.3.13 Current Monitor, Programmable Current Limit, and Current Loop Error Amplifier (IMON/ILIM, ISET)
      14. 6.3.14 Dual Loop Architecture
      15. 6.3.15 PWM Comparator
      16. 6.3.16 Slope Compensation
      17. 6.3.17 High-Side and Low-Side Gate Drivers (HO, LO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM Mode and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 High Efficiency 400kHz CC-CV Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With Excel Quickstart Tool
          2. 7.2.1.2.2 Recommended Components
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate-Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Connect the exposed pad to AGND and PGND on the PCB.
Figure 4-1 19-Pin VQFN RGY Package With Wettable Flanks(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 ISET ­­I/O Dynamic current setting pin for the constant current operation
2 RT ­­I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz and DRSS disabled. A resistor from RT to VCC sets the oscillator frequency between 100kHz and 2.2MHz and DRSS enabled.
3 COMP O Transconductance error amplifier output. Connect the compensation network from COMP to AGND.
4 FB I Connect FB to VCC to set the output voltage to pre-programmed fixed 12V. Connect FB to AGND to set the output voltage to pre-programmed fixed 5V. Alternatively, install a resistor divider from VOUT to AGND to set the output voltage setpoint between 0.8V and 80V. The FB regulation voltage is 0.8V.
5 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
6 IMON/ILIM O Current monitor and current limit programming pin
7 VCC P VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND.
8 PGND G Power ground connection pin for low-side MOSFET gate driver.
9 LO O Low-side power MOSFET gate driver output.
10 VIN P Supply voltage input source for the VCC regulator.
11 HO O High-side power MOSFET gate driver output.
12 SW P Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
13 CBOOT P High-side driver supply for bootstrap gate drive.
14 BIAS P Optional supply voltage input source for VCC regulator. This input takes over if VBIAS > 9V (typcial) and VIN supply is disabled.
15 PGOOD O Power-good pin. An open-collector output that goes low if VOUT is outside the specified regulation window.
16 FPWM/SYNC I Connect FPWM/SYNC to VCC to enable forced PWM (FPWM) mode with continuous conduction at light loads. Connect FPWM/SYNC to AGND to operate the LM5190-Q1 in diode emulation mode. FPWM/SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock signal.
17 EN I An active-high precision input with rising threshold of 1V and hysteresis voltage of 100mV. If the EN voltage is less than 0.55V, the LM5190-Q1 is in shutdown mode.
18 ISNS+ I Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor using a low-current Kelvin connection.
19 VOUT I Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current sense resistor.
(1) P = Power, G = Ground, I = Input, O = Output