SNVSAW8E March   2020  – April 2022 LM62440-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Characteristics
    7. 8.7 Systems Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  EN Uses for Enable and VIN UVLO
      2. 9.3.2  MODE/SYNC Pin Operation
        1. 9.3.2.1 Level-Dependent MODE/SYNC Pin Control
        2. 9.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
        3. 9.3.2.3 Clock Locking
      3. 9.3.3  PGOOD Output Operation
      4. 9.3.4  Internal LDO, VCC UVLO, and BIAS Input
      5. 9.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      6. 9.3.6  Adjustable SW Node Slew Rate
      7. 9.3.7  Spread Spectrum
      8. 9.3.8  Soft Start and Recovery From Dropout
      9. 9.3.9  Output Voltage Setting
      10. 9.3.10 Overcurrent and Short Circuit Protection
      11. 9.3.11 Thermal Shutdown
      12. 9.3.12 Input Supply Current
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 Auto Mode – Light-Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode – Light-Load Operation
        4. 9.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 9.4.3.5 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Choosing the Switching Frequency
        2. 10.2.2.2  Setting the Output Voltage
        3. 10.2.2.3  Inductor Selection
        4. 10.2.2.4  Output Capacitor Selection
        5. 10.2.2.5  Input Capacitor Selection
        6. 10.2.2.6  BOOT Capacitor
        7. 10.2.2.7  BOOT Resistor
        8. 10.2.2.8  VCC
        9. 10.2.2.9  BIAS
        10. 10.2.2.10 CFF and RFF Selection
        11. 10.2.2.11 External UVLO
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground and Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

GUID-490B2378-26E2-4B62-A853-F7804973CA7A-low.gif Figure 7-1 14-Pin VQFN-HRRJR Package(Top View)
Table 7-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
BIAS 1 P Input to internal LDO. Connect to the output voltage point to improve efficiency. Connect an optional high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity. If output voltage is above 12 V, connect this pin to ground.
VCC 2 O Internal LDO output. Used as a supply to internal control circuits. Do not connect to any external loads. Connect a high-quality 1-µF capacitor from this pin to AGND.
AGND 3 G Analog ground for internal circuitry. Feedback and VCC are measured with respect to this pin. Must connect AGND to both PGND1 and PGND2 on PCB.
FB 4 I Output voltage feedback input to the internal control loop. Connect to the output voltage sense point for fixed 3.3-V or 5-V output voltage factory options. Connect to the feedback divider tap point for adjustable output voltage. Do not float or connect to ground.
PGOOD 5 O Open-drain power-good status output. Pull this pin up to a suitable voltage supply through a current limiting resistor. High = power OK, low = fault. PGOOD output goes low when EN = low, VIN > 1 V.
MODE/SYNC 6 I This pin controls the mode of operation of the LM62440-Q1. Modes include auto mode (automatic PFM and PWM operation), FPWM, and synchronization to an external clock. When synchronized, the clock triggers on the rising edge of an external clock. Also, spread spectrum operation is controlled by this pin. See Section 9.3.2. Do not float this pin.
EN 7 I Precision enable input. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. See Section 10.
VIN1 8 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. Low impedance connection must be provided to VIN2.
PGND1 9 G Power ground to the internal low-side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
SW 10 O Switch node of the converter. Connect to the output inductor.
PGND2 11 G Power ground to the internal low-side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
VIN2 12 P Input supply to the converter. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. Low impedance connection must be provided to VIN1.
RBOOT 13 I/O Connect to CBOOT through a resistor. This resistance must be between 0 Ω and open. This resistance determines SW node rise time.
CBOOT 14 I/O High-side driver upper supply rail. Connect a 100-nF capacitor between SW and CBOOT. An internal diode connects to VCC and allows CBOOT to charge while SW node is low.