See(1)(2)(3)Supply Voltage, VDD | −0.3 V to 6.0 V |
Voltage on SMBDAT, SMBCLK,
ALERT,
T_Crit, PWM Pins | −0.5 V to 6.0 V |
Voltage on Other Pins | −0.3 V to (VDD + 0. 3 V) |
Input Current, D− Pin | ±1 mA |
Input Current at All Other Pins (4) | 5 mA |
Package Input Current (4) | 30 mA |
Package Power Dissipation SMBDAT,
ALERT,
T_Crit, PWM pins | See (5) |
Output Sink Current | 10 mA |
Storage Temperature | −65°C to +150°C |
ESD Susceptibility(6) | Human Body Model | 2000 V |
Machine Model | 200 V |
SMT Soldering Information See AN-1187 (SNOA401Q), "Leadless Leadframe Package" for information on SMT Assembly using LLP Packages. |
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND, unless otherwise noted.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) When the input voltage (V
IN) at any pin exceeds the power supplies (V
IN < GND or V
IN > V+), the current at that pin should be limited to 5 mA. Parasitic components and/or ESD protection circuitry are shown in the
Table 5-1, for the LM64's pins, by an "X" when it exists. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D−. Doing so by more than 50 mV may corrupt temperature measurements.
(5) See AN-1187
SNOA401 for Thermal Resistance
Junction-to-Ambient Temperature.
(6) Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. See
Figure 5-2 for the ESD Protection Input Structure.