SNVSCD2 September   2024 LM704A0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
      3. 6.3.3  Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On-Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Shunt Current Sensing
      13. 6.3.13 Hiccup Mode Current Limiting
      14. 6.3.14 Device Configuration (CONFIG)
      15. 6.3.15 Single-Output Dual-Phase Operation
      16. 6.3.16 Pulse Frequency Modulation (PFM) / Synchronization
      17. 6.3.17 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Active Mode
      4. 6.4.4 Sleep Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
      3. 7.1.3 Maximum Ambient Temperature
        1. 7.1.3.1 Derating Curves
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency, Wide Input, 400kHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 7.2.1.2.3 Buck Inductor
          4. 7.2.1.2.4 Current-Sense Resistance
          5. 7.2.1.2.5 Output Capacitors
          6. 7.2.1.2.6 Input Capacitors
          7. 7.2.1.2.7 Frequency Set Resistor
          8. 7.2.1.2.8 Feedback Resistors
          9. 7.2.1.2.9 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High Efficiency 24V to 3.3V 400kHz Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Design and Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.15 Single-Output Dual-Phase Operation

For single-output, dual-phase operation, two LM704A0-Q1 devices are required. Additional phases cannot be added. Configure the first device as a primary and the second device as a secondary per Table 6-2. This action disables the feedback error amplifier of the secondary device and places feedback error amplifier into a high-impedance state. Connect EXTCOMP pins of the primary and secondary devices together with minimal trace length. Add an external compensation network near the primary device. Internal compensation feature is not supported when operating in dual-phase configuration. The PG / SYNCOUT pin of the primary device must be connected to the PFM / SYNCIN pin of the secondary device. The SYNCOUT of the primary device is 180° out-of-phase and facilitates the interleaved operation. RT pin is not used for the oscillator when the LM704A0-Q1 is configured as a secondary device but instead is used for the slope compensation. RT resistance on the secondary device needs to be the same value as RT resistance on the primary device to make sure of correct operation. The oscillator frequency is derived from the primary device. When operating in Interleaved mode, both devices need to be enabled at the exact same time for start-up. After the regulator has started, pull the secondary EN pin low (< 0.8V) for phase shedding if needed at light load to increase the efficiency.

Configure PFM mode by connecting both the PFM/SYNC pin of the primary and the FB pin of the secondary to the VDDA pin as shown in Figure 6-6.

LM704A0-Q1 Simplified Schematic for Single-Output Dual-Phase Operation in PFM Mode Figure 6-6 Simplified Schematic for Single-Output Dual-Phase Operation in PFM Mode

Configure FPWM mode by applying an external synchronization signal to the PFM/SYNCIN pin of the primary or connecting the pin to the AGND and connecting the FB pin of the secondary to the AGND pin as shown in Figure 6-7.

LM704A0-Q1 Simplified Schematic for Single-Output Dual-Phase Operation in FPWM Mode Figure 6-7 Simplified Schematic for Single-Output Dual-Phase Operation in FPWM Mode

Note: While in interleaved mode, if an external SYNCIN signal is applied after the start-up, there is a 2 clock cycle delay before the LM704A0-Q1 locks onto the external sync signal.

In PFM mode, while the primary device is pulse skipping to reduce the IQ-SLEEP current, the primary device disables the synchronization clock output, therefore the phase shedding is not supported. Phase shedding is only supported in FPWM.

When operating in PFM mode under light load conditions, either primary device or secondary device or both devices can switch.

In FPWM mode, the secondary device can be disabled to reduce the IQ-SLEEP current, and then the device can be enabled to support higher load currents when needed. When the secondary device enable is recycled the internal soft-start is pulled low, and then the LM704A0-Q1 goes through a normal soft-start turn-on. During the secondary soft-start time (2.8ms typical) there is a phase current imbalance until the soft-start is done. The phase current imbalance is also possible when in dropout as there is no control over the current. Matching the impedance of the outputs of the primary and secondary devices minimizes the phase current imbalance.

For more information, see Benefits of a Multiphase Buck Converter and Multiphase Buck Design From Start to Finish.