SNOSDB8A June   2021  – December 2021 LM74701-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage
      2. 8.3.2 Charge Pump
      3. 8.3.3 Gate Driver
      4. 8.3.4 Enable
      5. 8.3.5 Battery Voltage Monitoring (SW)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Conduction Mode
        1. 8.4.2.1 Regulated Conduction Mode
        2. 8.4.2.2 Full Conduction Mode
        3. 8.4.2.3 VDS Clamp Mode
      3. 8.4.3 Reverse Current Protection Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 MOSFET Selection
        3. 9.2.2.3 Charge Pump VCAP (CVCAP) and Input Capacitance (CIN)
        4. 9.2.2.4 Output Capacitance (COUT)
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
    4. 9.4 OR-ing Application Configuration
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4 OR-ing Application Configuration

Basic redundant power architecture comprises of two or more voltage or power supply sources driving a single load. In its simplest form, the OR-ing solution for redundant power supplies consists of Schottky OR-ing diodes that protect the system against an input power supply fault condition. A diode OR-ing device provides effective and low cost solution with few components. However, the diodes forward voltage drops affects the efficiency of the system permanently, because each diode in an OR-ing application spends most of its time in forward conduction mode. These power losses increase the requirements for thermal management and allocated board space.

The LM74701-Q1 ICs combined with external N-Channel MOSFETs can be used in OR-ing Solution as shown in Figure 9-12. The forward diode drop is reduced as the external N-Channel MOSFET is turned ON during normal operation. LM74701-Q1 quickly detects the reverse current, pulls down the MOSFET gate fast, leaving the body diode of the MOSFET to block the reverse current flow. An effective OR-ing solution must be extremely fast to limit the reverse current amount and duration. The LM74701-Q1 devices in OR-ing configuration constantly sense the voltage difference between Anode and Cathode pins, which are the voltage levels at the power sources (VIN1, VIN2) and the common load point respectively. The source to drain voltage VDS for each MOSFET is monitored by the Anode and Cathode pins of the LM74701-Q1. A fast comparator shuts down the gate drive through a fast pulldown within 0.45 μs (typical) as soon as V(IN) – V(OUT) falls below –11 mV. The fast comparator turns on the Gate with 11 mA gate charge current after the differential forward voltage V(IN) – V(OUT) exceeds 50 mV.

GUID-20211118-SS0I-M6JL-FKQK-0DKPSCSGWN43-low.gifFigure 9-12 Typical OR-ing Application

Figure 9-13 to Figure 9-16 show the smooth switch over between two power supply rails VIN1 at 12 V and VIN2 at 15 V. Figure 9-17 and Figure 9-18 illustrate the performance when VIN2 fails. LM74701-Q1 controlling VIN2 power rail turns off quickly, so that the output remains uninterrupted and VIN1 is protected from VIN2 failure.

GUID-20210915-SS0I-CZBL-DDFR-FNQJGG53RMHT-low.png
Time (10 ms/DIV)
Figure 9-13 ORing VIN1 to VIN2 Switch Over
GUID-20210915-SS0I-0M1T-XBWB-JQPR0RXX2J7S-low.png
Time (10 ms/DIV)
Figure 9-15 ORing VIN2 to VIN1 Switch Over
GUID-20210915-SS0I-SBH7-RMS8-4L3NSCRDQZQ7-low.png
Time (10 ms/DIV)
Figure 9-17 ORing - VIN2 Failure and Switch Over to VIN1
GUID-20210915-SS0I-KC2D-TSLP-CWGZJMVDVZMM-low.png
Time (20 ms/DIV)
Figure 9-14 ORing VIN1 to VIN2 Switch Over
GUID-20210915-SS0I-TVBV-LHN6-BPGLD9WBNNTW-low.png
Time (10 ms/DIV)
Figure 9-16 ORing VIN2 to VIN1 Switch Over
GUID-20210915-SS0I-HTGP-229C-V9DSMBJH8VDD-low.png
Time (20 ms/DIV)
Figure 9-18 ORing - VIN2 Failure and Switch Over to VIN1

LM74701-Q1 has VDS clamp mode of operation where device detects the voltage difference between CATHODE and ANODE and turns on the external FET in active clamp region when the V(OUT) – V(IN) crosses the VDSCLAMP threshold. So LM74701-Q1 can be used in ORing applications where worst case V(OUT) – V(IN) is less than device VDSCLAMP minimum specification as mentioned in the Electrical Characteristics table.