SNVSAU3B December   2017  – October 2019 LM76002-Q1 , LM76003-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
    2.     Efficiency vs Output Current (VOUT = 5 V, fSW = 400 kHz, Auto Mode)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current-Mode Control
      2. 7.3.2  Light Load Operation Modes — PFM and FPWM
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (EN Pin) and UVLO
      5. 7.3.5  Internal LDO, VCC UVLO, and Bias Input
      6. 7.3.6  Soft Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Adjustable Switching Frequency (RT) and Frequency Synchronization
      8. 7.3.8  Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage and VBOOT UVLO (BOOT Pin)
      11. 7.3.11 Power Good and Overvoltage Protection (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 DCM Mode
      6. 7.4.6 Light Load Mode
      7. 7.4.7 Foldback Mode
      8. 7.4.8 Forced Pulse-Width-Modulation Mode
      9. 7.4.9 Self-Bias Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feed-Forward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitors
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
        14. 8.2.2.14 Synchronization
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Highlights
      2. 10.1.2 Compact Layout for EMI Reduction
      3. 10.1.3 Ground Plane and Thermal Considerations
      4. 10.1.4 Feedback Resistors
    2. 10.2 Layout Example
    3. 10.3 Thermal Design
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Adjustable Output Voltage

The voltage regulation loop in the LM76002-Q1/LM76003-Q1 regulates the FB voltage to be the same as the internal reference voltage. The output voltage of the LM76002-Q1/LM76003-Q1 is set by a resistor divider to program the ratio from VOUT to VFB. The resistor divider is connected from the output node to ground with the mid-point connecting to the FB pin.

LM76002-Q1 LM76003-Q1 output_voltage_setting.gifFigure 11. Output Voltage Setting

The voltage reference system produces a precise ±1% voltage reference over temperature. TI recommends using divider resistors with 1% tolerance or better with temperature coefficient of 100 ppm or lower. Selection of RFBT equal or lower than 100 kΩ is also recommended. RFBB can be calculated by Equation 1:

Equation 1. LM76002-Q1 LM76003-Q1 eq01_snvsak0.gif

Larger RFBT and RFBB values reduce the current that goes through the divider, thus helping to increase light load efficiency. However, larger values also make the feedback path more susceptible to noise. If efficiency at very light load is not critical in a certain application, TI recommends RFBT = 10 kΩ to 100 kΩ. If the resistor divider is not connected properly, output voltage cannot be regulated because the feedback loop is broken. If the FB pin is shorted to ground or disconnected, the output voltage is driven close to VIN because the regulator detects very low voltage on the FB node. The load connected to VOUT could be damaged in this case. It is important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout.

The minimum output voltage achievable equals VFB, with RFBB open. The maximum VOUT is limited by the maximum duty cycle at a given frequency:

Equation 2. DMAX = 1 – (tOFF_MIN / TSW)

where

  • tOFF_MIN is the minimum off time of the HS switch
  • TSW = 1 / fSW is the switching period

Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX

Maximum output voltage with frequency foldback can be estimated using Equation 3:

Equation 3. LM76002-Q1 LM76003-Q1 eq_maximum_outputvoltage_Tonmax2.gif