SNVSBK6A February   2020  – July 2020 LM76005-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Peak-Current-Mode Control
      2. 7.3.2  Light Load Operation Modes — PFM and FPWM
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (EN Pin) and UVLO
      5. 7.3.5  Internal LDO, VCC UVLO, and Bias Input
      6. 7.3.6  Soft Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Adjustable Switching Frequency (RT) and Frequency Synchronization
      8. 7.3.8  Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Bootstrap Voltage and VBOOT UVLO (BOOT Pin)
      10. 7.3.10 Power Good and Overvoltage Protection (PGOOD)
      11. 7.3.11 Overcurrent and Short-Circuit Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 DCM Mode
      6. 7.4.6 Light Load Mode
      7. 7.4.7 Foldback Mode
      8. 7.4.8 Forced Pulse-Width-Modulation Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feedforward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitors
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
        14. 8.2.2.14 Synchronization
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Highlights
      2. 10.1.2 Compact Layout for EMI Reduction
      3. 10.1.3 Ground Plane and Thermal Considerations
      4. 10.1.4 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Support Resources
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 400 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (PVIN PINS)
VIN Operating input voltage range 3.5 60 V
ISD Shutdown quiescent current; measured at PVIN pin(1) VEN = 0 V 1.2 10 µA
IQ_NONSW Operating quiescent current from VIN (non-switching) VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external 2 12 µA
ENABLE (EN PIN)
VEN_VCC_H Enable input high level for VCC output VEN rising 1.2 V
VEN_VCC_L Enable input low level for VCC output VEN falling 0.3 V
VEN_VOUT_H Enable input high level for VOUT VEN rising 1.14 1.204 1.25 V
VEN_VOUT_HYS Enable input hysteresis for VOUT VEN falling hysteresis –150 mV
ILKG_EN Enable input leakage current VEN = 2 V 1.4 200 nA
INTERNAL LDO (VCC PIN, BIAS PIN)
VCC Internal VCC voltage PWM operation 3.29 V
PFM operation 3.1 V
VCC_UVLO Internal VCC undervoltage lockout VCC rising 2.96 3.14 3.27 V
VCC falling hysteresis –565 mV
VBIAS_ON Input change over VBIAS rising 3.11 3.25 V
VBIAS falling hysteresis –63 mV
IBIAS_NONSW Operating quiescent current from external VBIAS (non-switching) VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external 21 50 µA
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage PWM mode 0.987 1.006 1.017 V
ILKG_FB Input leakage current at FB pin VFB = 1 V 0.2 60 nA
HIGH SIDE DRIVER (BOOT PIN)
VBOOT_UVLO BOOT - SW undervoltage lockout 1.6 2.2 2.7 V
CURRENT LIMITS AND HICCUP
IHS_LIMIT​​​​​​(2) Short-circuit, high-side current limit 6.0 6.8 7.8 A
ILS_LIMIT (2) Low-side current limit 4.5 5.1 5.8 A
INEG_LIMIT Negative current limit –4.1 A
VHICCUP Hiccup threshold on FB pin 0.38 0.42 0.46 V
IL_ZC Zero cross-current limit 0.05 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.8 2 2.2 µA
RSSD Soft-start discharge resistance UVLO, TSD, OCP; or EN = 0 V 2 kΩ
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
VPGOOD_OV Power-good overvoltage threshold % of FB voltage 106% 110% 113%
VPGOOD_UV Power-good undervoltage threshold % of FB voltage 86% 90% 93%
VPGOOD_HYS Power-good hysteresis % of FB voltage 2.5%
VPGOOD_VALID Minimum input voltage for proper PGOOD function 50-µA pullup to PGOOD pin, VEN = 0 V 1.3 2 V
RPGOOD Power-good on-resistance VEN = 2.5 V 40 100 Ω
VEN = 0 V 30 90
MOSFETS
RDS_ON_HS (3) High-side MOSFET on-resistance IOUT  = 1 A, VBIAS = VOUT = 3.3 V 95 150 mΩ
RDS_ON_LS (3) Low-side MOSFET on-resistance IOUT  = 1 A, VBIAS = VOUT = 3.3 V 45 85 mΩ
THERMAL SHUTDOWN
TSD (4) Thermal shutdown threshold Shutdown threshold 150 °C
Recovery threshold 135 °C
(1) Shutdown current includes leakage current of the switching transistors.
(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.
(3) Measured at pins.
(4) Ensured by design.