SNOSC51D March   1998  – February 2024 LMC660 , LMC662

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC662
    5. 5.5 Thermal Information LMC660
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Amplifier Topology
      2. 6.1.2 Compensating Input Capacitance
      3. 6.1.3 Capacitive Load Tolerance
      4. 6.1.4 Bias Current Testing
    2. 6.2 Typical Applications
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Printed Circuit Board Layout for High-Impedance Work
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3.     Trademarks
    4. 7.3 Electrostatic Discharge Caution
    5. 7.4 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Typical Characteristics

at TA = 25°C, VS = ±7.5V, VOUT = mid-supply, RL≥ 1MΩ (unless otherwise specified)

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Figure 5-1 Supply Current vs Supply Voltage
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Figure 5-3 Offset Voltage vs Common-Mode Voltage
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Figure 5-5 Input Bias Current vs Input Common-Mode Voltage
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Figure 5-7 Output Characteristics Current Sinking
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Figure 5-9 Input Voltage Noise vs Frequency
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Figure 5-11 Open-Loop Frequency Response
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Figure 5-13 Noninverting Large-Signal Pulse Response
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Avoid resistive loads < 500Ω because of possible instability
Figure 5-15 Stability vs Capacitive Load
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Figure 5-2 Offset Voltage
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Figure 5-4 Input Bias Current
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VS = ±2.5V  
Figure 5-6 Input Bias Current vs Input Common-Mode Voltage
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Figure 5-8 Output Characteristics Current Sourcing
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Figure 5-10 CMRR vs Frequency
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Figure 5-12 Frequency Response vs Capacitive Load
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Avoid resistive loads < 500Ω because of possible instability
Figure 5-14 Stability vs Capacitive Load