SNOSDF9B July   2023  – March 2024 LMG2100R044

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Slew Rate Control
        4. 8.2.2.4 Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RAR|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
ICC VCC Quiescent Current LI = HI = 0V, VCC = 5V 0.09 0.2 mA
ICC VCC Quiescent Current LI=VCC=5V, HI=0V 0.460 4.5 mA
ICCO Total VCC Operating Current f = 500 kHz, 50% Duty cycle, VIN = 48V 7.5 15 mA
IHB HB Quiescent Current LI = HI = 0V, VCC = 5V, HB-HS = 4.6V 0.1 0.2 mA
IHB HB Quiescent Current LI=0V, HI=VCC=5V, HB-HS=4.6V 0.23 4.5 mA
IHBO HB Operating Current f = 500 kHz, 50% Duty cycle, VCC = 5V, HB-HS = 4.6V 3.5 7.5 mA
INPUT PINS
VIH High-Level Input Voltage Threshold Rising Edge 1.87 2.06 2.22 V
VIL Low-Level Input Voltage Threshold Falling Edge 1.48 1.66 1.76 V
VHYS Hysteresis between rising and falling threshold 400 mV
RI Input pull down resistance 100 200 300 kΩ
UNDER VOLTAGE PROTECTION
VCCR VCC Rising edge threshold Rising 3.2 3.8 4.5 V
VCCF VCC Falling edge threshold 3.0 3.6 4.3 V
VCC(hyst) VCC UVLO threshold hysteresis 210 mV
VHBR HB Rising edge threshold Rising 2.5 3.2 3.9 V
VHBF HB Falling edge threshold 2.3 3.0 3.7 V
VHB(hyst) HB UVLO threshold hysteresis 200 mV
BOOTSTRAP DIODE
VDL Low-Current forward voltage IHB-HS = 100µA 0.45 0.7 V
VDH High current forward voltage IHB-HS = 100mA 0.9 1.0 V
RD Dynamic Resistance IHB-HS = 100mA 1.85 Ω
HB-HS Clamp Regulation Voltage 4.65 5 5.2 V
tBS Bootstrap diode reverse recovery time IF = 100 mA, IR = 100 mA 40 ns
QRR Bootstrap diode reverse recovery charge VVIN = 50 V 2 nC
POWER STAGE
RDS(ON)HS High-side GaN FET on-resistance LI=0V, HI=VCC=5V, HB-HS=5V, I(VIN-SW)=16A, TJ = 25℃ 4.4 6.0 mΩ
RDS(ON)LS Low-side GaN FET on-resistance LI=VCC=5V, HI=0V, HB-HS=5V, I(SW-PGND)=16A, TJ = 25℃ 4.3 5.7 mΩ
VSD GaN 3rd quadrant conduction drop ISD = 500 mA, VIN floating, VCC = 5 V, HI = LI = 0V 1.5 V
IL-VIN-SW Leakage from VIN to SW when the high-side GaN FET and low-side GaN FET are off VIN = 80V, SW=0, HI = LI = 0V, VCC = 5V, TJ=25℃ 4 80 µA
IL-SW-GND Leakage from SW to GND when the high-side GaN FET and low-side GaN FET are off SW = 80V, HI = LI = 0V, VCC = 5V, TJ=25℃ 4 80 µA
CISS Input Capacitance of high side or low side HEMT VDS=50V, VGS= 0V (HI = LI = 0V) 1046 1348 pF
COSS Output Capacitance of high-side GaN FET or low-side GaN FET VDS=50V, VGS= 0V (HI = LI = 0V) 364 478 pF
COSS(ER) Output Capacitance of high-side GaN FET or low-side GaN FET - Energy Related VDS=0 to 50V, VGS= 0V (HI = LI = 0V) 441 pF
COSS(TR) Output Capacitance of high-side GaN FET or low-side GaN FET - Time Related VDS=0 to 50V, VGS= 0V (HI = LI = 0V) 548 pF
CWELL HV-Well Capacitance (SW to PGND) VIN=VSW=50V, HI = LI = 0V 30 pF
CRSS Reverse Transfer Capacitance of high side or low side HEMT VDS=50V, VGS= 0V (HI = LI = 0V) 2.9 pF
QG Total Gate Charge of high side or low side HEMT VDS=50V, ID= 16A, VGS= 5V 7.3 9.3 nC
QGD Gate to Drain Charge of high side or low side HEMT VDS=50V, ID= 16A 0.7 nC
QGS Gate to Source Charge of high side or low side HEMT VDS=50V, ID= 16A 2.8 nC
QOSS Output Charge (sum of high side HEMT, low side HEMT and gate-driver HV-Well charge)  VDS=50V, ID= 16A 55 80 nC
QRR Source to Drain Reverse Recovery Charge Not including internal driver bootstrap diode 0 nC
tHIPLH Propagation delay: HI Rising(2) LI=0V, VCC=5V, HB-HS=5V, VIN=48V 35 50 ns
tHIPHL Propagation delay: HI Falling(2) LI=0V, VCC=5V, HB-HS=5V, VIN=48V 33 50 ns
tLPLH Propagation delay: LI Rising(2) HI=0V, VCC=5V, HB-HS=5V, VIN=48V 35 50 ns
tLPHL Propagation delay: LI Falling(2) HI=0V, VCC=5V, HB-HS=5V, VIN=48V 33 50 ns
tMON Delay Matching: LI high & HI low(2) 2 8.0 ns
tMOFF Delay Matching: LI low & HI high(2) 2 8.0 ns
tPW Minimum Input Pulse Width that Changes the Output 10 ns
(1) Parameters that show only a typical value are determined by design and may not be tested in production
(2) See Propagation Delay and Mismatch Measurement section