SNOSDH5 November 2024 LMG2640
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 6-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a double-pulse tester. Consult external references for double-pulse tester details. The circuit is placed in the boost configuration to measure the low-side GaN switching parameters. The circuit is placed in the buck configuration to measure the high-side GaN switching parameters. The GaN FET not being measured in each configuration (high-side in the boost and low-side in the buck) acts as the double-pulse tester diode and circulates the inductor current in the off-state, third-quadrant conduction mode. Table 6-1 shows the details for each configuration.
Configuration | GaN FET Under Test | GaN FET Acting as Diode | SBOOST | SBUCK | VINL | VINH |
---|---|---|---|---|---|---|
Boost | Low-side | High-side | Closed | Open | Double-pulse waveform | 0V |
Buck | High-side | Low-side | Open | Closed | 0V | Double-pulse waveform |
Figure 6-2 shows the GaN power FET switching parameters.
The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and turn-on rise time. Note that the turn-on rise time is the same as the VDS 80% to 20% fall time.
The GaN power FET turn-off transition has two timing components: turn-off delay time, and turn-off fall time. Note that the turn-off fall time is the same as the VDS 20% to 80% rise time. The turn-off timing components are heavily dependent on the LHB current.
The turn-on slew rate is measured over a smaller voltage delta (100V) compared to the turn-on rise time voltage delta (240V) to obtain a faster slew rate which is useful for EMI design.