SNOSDH5 November   2024 LMG2640

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Current-Sense Emulation
      3. 7.3.3  Bootstrap Diode Function
      4. 7.3.4  Input Control Pins (EN, INL, INH)
      5. 7.3.5  INL - INH Interlock
      6. 7.3.6  AUX Supply Pin
        1. 7.3.6.1 AUX Power-On Reset
        2. 7.3.6.2 AUX Under-Voltage Lockout (UVLO)
      7. 7.3.7  BST Supply Pin
        1. 7.3.7.1 BST Power-On Reset
        2. 7.3.7.2 BST Under-Voltage Lockout (UVLO)
      8. 7.3.8  Over-Current Protection
      9. 7.3.9  Over-Temperature Protection
      10. 7.3.10 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRG|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage; ID(hs) = DH to SW current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; 10V ≤ VAUX ≤ 26V; 7.5V ≤ VBST_SW ≤ 26V; VEN = 5V; VINL = 0V; VINH = 0V; RCS = 100Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW-SIDE GAN POWER FET
td(on)(Idrain)(ls) Drain current turn-on delay time From VINL > VINL,IT+ to ID(ls) > 50mA, VBUS = 400V, LHB current = 2.5A 33 ns
td(on)(ls) Turn-on delay time From VINL > VINL,IT+ to VDS(ls) < 320V, VBUS = 400V, LHB current = 2.5A 39 ns
tr(on)(ls) Turn-on rise time From VDS(ls) < 320V to VDS(ls) < 80V, VBUS = 400V, LHB current = 2.5A 2.4 ns
td(off)(ls) Turn-off delay time From VINL < VINL,IT– to VDS(ls) > 80V, VBUS = 400V, LHB current = 2.5A 40 ns
tf(off)(ls) Turn-off fall time From VDS(ls) > 80V to VDS(ls) > 320V, VBUS = 400V, LHB current = 2.5A 16.0 ns
Turn-on slew rate From VDS(ls) < 250V to VDS(ls) < 150V, TJ = 25℃, VBUS = 400V, LHB current = 2.5A 125 V/ns
HIGH-SIDE GAN POWER FET
td(on)(Idrain)(hs) Drain current turn-on delay time From VINH > VINH,IT+ to ID(hs) > 50mA, VBUS = 400V, LHB current = 2.5A 33 ns
td(on)(hs) Turn-on delay time From VINH > VINH,IT+ to VDS(hs) < 320V, VBUS = 400V, LHB current = 2.5A 39 ns
tr(on)(hs) Turn-on rise time From VDS(hs) < 320V to VDS(hs) < 80V, VBUS = 400V, LHB current = 2.5A 2.4 ns
td(off)(hs) Turn-off delay time From VINH < VINH,IT– to VDS(hs) > 80V, VBUS = 400V, LHB current = 2.5A 40 ns
tf(off)(hs) Turn-off fall time From VDS(hs) > 80V to VDS(hs) > 320V, VBUS = 400V, LHB current = 2.5A 16.0 ns
Turn-on slew rate From VDS(hs) < 250V to VDS(hs) < 150V, TJ = 25℃, VBUS = 400V, LHB current = 2.5A 125 V/ns
LOW-SIDE OVERCURRENT PROTECTION
t(OC)(ls) Overcurrent fault response time, FET on before overcurrent From ID(ls) > IT(OC)(ls) to ID(ls) < 0.5 × IT(OC)(ls), at following ID(ls) slew rate
ID(ls) di/dt = 12 A/µs 175 ns
ID(ls) di/dt = 24 A/µs 150 ns
ID(ls) di/dt = 120 A/µs 90
t(OC)(en)(ls) Overcurrent fault response time, FET enabled into a short VDS(ls) = 50 V; From ID(ls) > IT(OC)(ls) to ID(ls) < 0.5 × IT(OC)(ls) 122 ns
HIGH-SIDE OVERCURRENT PROTECTION
t(OC)(hs) Overcurrent fault response time, FET on before overcurrent From ID(hs) > IT(OC)(hs) to ID(hs) < 0.5 × IT(OC)(hs), at following ID(hs) slew rate
ID(hs) di/t = 12 A/µs 175 ns
ID(hs) di/t = 24 A/µs 150 ns
ID(hs) di/dt = 120 A/µs 90
t(OC)(en)(hs) Overcurrent fault response time, FET enabled into a short VDS(hs) = 50 V; From ID(hs) > IT(OC)(hs) to ID(hs) < 0.5 × IT(OC)(hs) 122 ns
CS
tr Rise time From ICS(src) > 0.1 × ICS(src)(final) to ICS(src) > 0.9 × ICS(src)(final), 0V ≤ VCS ≤ 2V, Low-side enabled into a 2.5A load 35 ns
EN
EN wake-up time From VEN > VIT+ to ID(ls) > 10mA, VINL = 5V 1.5 µs
BST
Start-up time from deep BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high-side reacts to INH rising edge with VBST_SW rising from 0V to 10V in 1µs 5 µs
Start-up time from shallow BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high-side reacts to INH rising edge with VBST_SW rising from 5V to 10V in 0.5µs 2 µs