SLUSF82B January   2024  – November 2024 LMG3100R017 , LMG3100R044

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Slew Rate Control
        4. 8.2.2.4 Use With Analog Controllers
        5. 8.2.2.5 Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • VBE|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

LMG3100R017 LMG3100R044 VBE Package,15-Pin VQFN(Top View)Figure 4-1 VBE Package,15-Pin VQFN(Top View)
Table 4-1 Pin Functions
PINI/O(1)DESCRIPTION
NAMENO.
NC1, 5, 11–13, 15—Not connected internally. Leave floating.
LI2ILow-side gate driver control input.
VCC3P5V device power supply.
AGND4GAnalog ground.
SRC6PSource of GaN FET. Internally connected to AGND.
DRN7PDrain of GaN FET.
HS8PBootstrap voltage ground reference.
HB9PHigh-side gate driver bootstrap rail with HS as the ground reference.
HO10OLevel shifted high-side gate driver control output.
HI14IHigh-side gate driver control input.
(1) I = Input, O = Output, G = Ground, P = Power