SLUSEY6A September   2023  – May 2024 LMG3522R050 , LMG3526R050

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On Slew Rate
      4. 6.1.4 Zero-Voltage Detection Times
    2. 6.2 Safe Operation Area (SOA)
      1. 6.2.1 Repetitive SOA
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3522R050 Functional Block Diagram
      2. 7.2.2 LMG3526R050 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN FET Operation Definitions
      2. 7.3.2  Direct-Drive GaN Architecture
      3. 7.3.3  Drain-Source Voltage Capability
      4. 7.3.4  Internal Buck-Boost DC-DC Converter
      5. 7.3.5  VDD Bias Supply
      6. 7.3.6  Auxiliary LDO
      7. 7.3.7  Fault Protection
        1. 7.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 7.3.7.2 Overtemperature Shutdown Protection
        3. 7.3.7.3 UVLO Protection
        4. 7.3.7.4 High-Impedance RDRV Pin Protection
        5. 7.3.7.5 Fault Reporting
      8. 7.3.8  Drive-Strength Adjustment
      9. 7.3.9  Temperature-Sensing Output
      10. 7.3.10 Ideal-Diode Mode Operation
        1. 7.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
      11. 7.3.11 Zero-Voltage Detection (ZVD)
    4. 7.4 Start-Up Sequence
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Slew Rate Selection
          1. 8.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 8.2.2.2 Signal Level-Shifting
        3. 8.2.2.3 Buck-Boost Converter Design
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Using an Isolated Power Supply
      2. 8.4.2 Using a Bootstrap Diode
        1. 8.4.2.1 Diode Selection
        2. 8.4.2.2 Managing the Bootstrap Voltage
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Solder-Joint Reliability
        2. 8.5.1.2 Power-Loop Inductance
        3. 8.5.1.3 Signal-Ground Connection
        4. 8.5.1.4 Bypass Capacitors
        5. 8.5.1.5 Switch-Node Capacitance
        6. 8.5.1.6 Signal Integrity
        7. 8.5.1.7 High-Voltage Spacing
        8. 8.5.1.8 Thermal Recommendations
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Export Control Notice
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE; –40℃ ≤ TJ ≤ 125℃; VDS = 520V; 9V ≤ VVDD ≤ 18V; VIN = 0V; RDRV connected to LDO5V;  LBBSW = 4.7µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER TRANSISTOR
RDS(on) Drain-source on resistance VIN = 5V, TJ = 25°C 43 55 mΩ
VIN = 5V, TJ = 125°C 73
VSD Third-quadrant mode source-drain voltage IS = 0.1A 3.8 V
IS = 15A 3 5.3
IDSS Drain leakage current VDS = 650V, TJ = 25°C 1 µA
VDS = 650V, TJ = 125°C 7
COSS Output capacitance VDS = 400V 148 pF
CO(er) Energy related effective output capacitance VDS = 0V to 400V 185 pF
CO(tr) Time related effective output capacitance 260 pF
QOSS Output charge 100 nC
QRR Reverse recovery charge 0 nC
VDD – SUPPLY CURRENTS
VDD quiescent current VVDD = 12V, VIN = 0V or 5V 700 1200 µA
VDD operating current VVDD = 12V, fIN  = 140kHz, soft-switching 9.7 11 mA
BUCK BOOST CONVERTER
VNEG output voltage VNEG sinking 40mA –14 V
IBBSW,PK(low) Peak BBSW sourcing current at low peak current mode setting
(peak external buck-boost inductor current)		 0.3 0.4 0.5 A
IBBSW,PK(high) Peak BBSW sourcing current at high peak current mode setting
(peak external buck-boost inductor current)		 0.8 1 1.2 A
High peak current mode setting enable – IN positive-going threshold frequency 280 420 515 kHz
LDO5V
Output voltage LDO5V sourcing 25mA 4.75 5 5.25 V
Short-circuit current 25 50 100 mA
IN
VIN,IT+ Positive-going input threshold voltage 1.7 1.9 2.45 V
VIN,IT- Negative-going input threshold voltage 0.7 1 1.3 V
Input threshold hysteresis 0.7 0.9 1.3 V
Input pull-down resistance VIN = 2V 100 150 200 kΩ
FAULT, OC/ZVD, TEMP – OUTPUT DRIVE
Low-level output voltage Output sinking 8mA 0.16 0.4 V
High-level output voltage Output sourcing 8mA, measured as
VLDO5V – VO		 0.2 0.45 V
VDD, VNEG – UNDERVOLTAGE LOCKOUT
VVDD,T+(UVLO) VDD UVLO – positive-going threshold voltage 6.4 7 7.6 V
VDD UVLO – negative-going threshold voltage 6 6.5 7.1 V
VDD UVLO – input threshold voltage hysteresis 510 mV
VNEG UVLO – negative-going threshold voltage –13.6 –13.0 –12.3 V
VNEG UVLO – positive-going threshold voltage –13.3 –12.75 –12.1 V
GATE DRIVER
Turn-on slew rate From VDS < 320V to VDS < 80V, RDRV disconnected from LDO5V, RRDRV = 300kΩ, TJ = 25℃, VBUS = 400V, LHB current = 10A, see Figure 6-1   15 V/ns
From VDS < 320V to VDS < 80V, RDRV tied to LDO5V, TJ = 25℃, VBUS = 400V, LHB current = 10A, see Figure 6-1    100 V/ns
From VDS < 320V to VDS < 80V, RDRV disconnected from LDO5V, RRDRV = 0Ω, TJ = 25℃, VBUS = 400V, LHB current = 10A, see Figure 6-1         150 V/ns
Maximum GaN FET switching frequency VNEG rising to > –13.25V, soft-switched, maximum switching frequency derated for VVDD < 9V  3.6 MHz
FAULTS
IT(OC) DRAIN overcurrent fault – threshold current 45 55 65 A
IT(SC) DRAIN short-circuit fault – threshold current 65 80 95 A
di/dtT(SC) di/dt threshold between overcurrent and short-circuit faults 150 A/µs
GaN temperature fault – postive-going threshold temperature 175 °C
GaN temperature fault – threshold temperature hysteresis 30 °C
Driver temperature fault – positive-going threshold temperature 185 °C
Driver temperature fault – threshold temperature hysteresis 20 °C
TEMP
Output frequency 4.5 9 14 kHz
Output PWM duty cycle GaN TJ = 150℃ 82 %
GaN TJ = 125℃ 58.5 64.6 70
GaN TJ = 85℃ 36.2 40 43.7
GaN TJ = 25℃ 0.3 3 6
IDEAL-DIODE MODE CONTROL
VT(3rd) Drain-source third-quadrant detection – threshold voltage –0.15 0 0.15 V
IT(ZC) Drain zero-current detection – threshold current 0℃ ≤ TJ ≤ 125℃ –0.2 0 0.2 A
–40℃ ≤ TJ ≤ 0℃ –0.35 0 0.35