SNOSDL1 December   2024 LMG3650R035

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-On Times
      2. 7.1.2 Turn-Off Times
      3. 7.1.3 Drain-Source Turn-On and Turn-off Slew Rate
      4. 7.1.4 Zero-Voltage Detection Times (LMG3656R035 only)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 LMG3650R035 Functional Block Diagram
      2. 8.2.2 LMG3651R035 Functional Block Diagram
      3. 8.2.3 LMG3656R035 Functional Block Diagram
      4. 8.2.4 LMG3657R035 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Drive Strength Adjustment
      2. 8.3.2 VDD Supply
      3. 8.3.3 Overcurrent and Short-Circuit Protection
      4. 8.3.4 Overtemperature Protection
      5. 8.3.5 UVLO Protection
      6. 8.3.6 Fault Reporting
      7. 8.3.7 Auxiliary LDO (LMG3651R035 Only)
      8. 8.3.8 Zero-Voltage Detection (ZVD) (LMG3656R035 Only)
      9. 8.3.9 Zero-Current Detection (ZCD) (LMG3657R035 Only)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
        2. 9.2.2.2 Signal Level-Shifting
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Using an Isolated Power Supply
      2. 9.3.2 Using a Bootstrap Diode
        1. 9.3.2.1 Diode Selection
        2. 9.3.2.2 Managing the Bootstrap Voltage
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • KLA|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND/SRC; –40℃ ≤ TJ ≤ 150℃; VDD = 12V; FLT/RDRV resistances R1 & R2 are open
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 0A, 100V/ns 30 45 ns
tir(on) Turn-on current rise time + delay time From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 10A, 100V/ns 35 60 ns
tvf(on) Turn-on voltage falling time From VDS < 320V to VDS < 80V, VBUS = 400V, LHB current = 10A, 100V/ns 1 2.3 3 ns
tvf_peak(on) Turn-on slew rate dv/dt when VDS = 200V, VBUS = 400V, LHB current = 10A, 100V/ns 90 115 150 V/ns
Pulse width distortion slew-rate setting at 100V/ns 20 ns
Minimum input pulse changing the output L-H-L slew-rate setting at 100V/ns such that SW crosses 200V 50 ns
td(off) Turn-off delay time at full speed From VIN < 2.5V to VDS >= 10V. VBUS = 400V, IL = 34A, fastest or full turn-off speed. 12 17 35 ns
tvr(off) Turn-off voltage rise time at full speed From VDS >= 20V to VDS >= 380V. VBUS = 400V, IL = 34A, fastest or full turn-off speed. 3 4.5 7 ns
STARTUP TIMES
TDRV_START Driver startup delay From Driver supply crossing UVLO to switch turning on if IN is high.  35 65 µs
FAULT TIMES
toff(OC) Overcurrent fault FET turn-off time, FET on before overcurrent From ID >= IT(OC) to Vds> 10V, di/dt = 100A/µs, in the fastest turn-off speed 370 480 ns
toff(OC_ON) Overcurrent total on time, turn-on into overcurrent. From Vds <= 10V to Vds >= 10V, turning on at 110% of OC level, at 100 V/ns turn-on slew rate and fastest turn-off speed. 420 580 ns
toff_cur(SC_ON) SC on time measured through drain current From LS Ids > 50A to Ids < 50A, at 100 V/ns turn-on slew rate in a half-bridge configuration. 100 500 ns
toff_cur(SC) SC response time with source current measurement From LS Vds>9V to LS Ids<50A, at 100 V/ns turn-on slew rate in a half-bridge configuration. . 300 ns
Latched-Fault reset time Time required to hold both gate driver input low to clear latched-fault 300 380 450 µs
ZCD/ZVD
ZCD delay Current crossing zero (low to high) to ZCD output pulse di/dt = 0.03A/ns 12 25 40 ns
ZVD delay In rising to ZVD output pulse. 100V/ns turn-on speed. 13 20 50 ns
tWD_ZVD ZVD pulse width Vbus = 10V, IL = 5A, measure ZVD pulse width 90 120 170 ns
ZVD sensing time Sensing time to fet turn on (100V/ns). IL=2A 11 25 ns