SNLS531B April   2016  – June 2018 LMH0324

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Pins
      2. 7.3.2 Carrier Detect
      3. 7.3.3 Adaptive Cable Equalizer
      4. 7.3.4 Launch Amplitude
      5. 7.3.5 Input-Output Mux Selection
      6. 7.3.6 Output Function Control
      7. 7.3.7 Output Driver Amplitude and De-Emphasis Control
      8. 7.3.8 Additional Programmability
        1. 7.3.8.1 Cable Length Indicator (CLI)
        2. 7.3.8.2 Digital MUTEREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH0324 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CableEQ/Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Recommended VOD and DE Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RTW Package
24-Pin QFN
Top View
LMH0324 pin_diagram_snls516.gif

Pin Functions

PIN I/O (1) DESCRIPTION
NAME NO.
High Speed Differential I/Os
IN0+ 1 I, Analog Single-ended complementary inputs, 75-Ω internal termination from IN0+ or IN0- to internal common mode voltage and return loss compensation network. Requires external 4.7-µF AC coupling capacitors for SMPTE video applications.
IN0- 2 I Analog
RSV1 4 Reserved pins.
Do not connect.
RSV2 5
OUT0+ 18 O, Analog Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user control.
OUT0- 17 O, Analog
OUT1+ 15 O, Analog Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user control.
OUT1- 14 O, Analog
Control Pins
CD_N 12 O, LVCMOS, OD CD_N is the carrier detect. CD_N is pulled LOW when signal is detected and adaptation is completed. CD_N is an open drain output. It requires an external resistor to logic supply.
CD_N is tolerant to 3.3 V when VDDIO is powered from 2.5 V supply.
IN_OUT_SEL 8 I, 4-LEVEL IN_OUT_SEL selects the signal flow at input port IN0 to output ports. See Table 2 for details. This pin setting can be overridden by register control.
OUT_CTRL 19 I, 4-LEVEL OUT_CTRL selects the equalized or un-equalized signal from IN0 to OUT0± and OUT1±. See Table 3 for details. This pin setting can be overridden by register control.
VOD_DE 11 I, 4-LEVEL VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0± and OUT1±. See Table 4 for details. This pin setting can be overridden by register control.
MODE_SEL 6 I, 4-LEVEL MODE_SEL enables SPI or SMBus serial control interface. See Table 5 for details.
Serial Control Interface (SPI Mode), MODE_SEL = F (Float)
SS_N 7 I, LVCMOS SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH0324 slave device. SS_N is a LVCMOS input referenced to VDDIO.
MISO 20 O, LVCMOS MISO is the SPI serial data output from the LMH0324 slave device. MISO is a LVCMOS output referenced to VDDIO.
MOSI 10 I, LVCMOS MOSI is used as the SPI serial data input to the LMH0324 slave device. MOSI is LVCMOS input referenced to VDDIO.
SCK 21 I, LVCMOS SCK is the SPI serial input clock to the LMH0324 slave device. SCK is LVCMOS referenced to VDDIO.
Serial Control Interface (SMBus MODE) , MODE_SEL = L (1 kΩ to VSS)
ADDR0 7 Strap, 4-LEVEL ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up.
ADDR1 20 Strap, 4-LEVEL
SDA 10 IO, LVCMOS, OD SMBus bi-directional open drain data line to or from the LMH0324 slave device. SDA is an open drain IO and requires an external 2 kΩ to 5 kΩ pull-up resistor to the SMBus termination voltage. SDA is 3.3 V tolerant when VDDIO is powered from 2.5 V.
SCL 21 I, LVCMOS, OD SMBus input clock to the LMH0324 slave device. It is driven by a LVCMOS open drain driver from the SMBus master. SCL requires an external 2 kΩ to 5 kΩ pull-up resistor to the SMBus termination voltage. SCL is 3.3 V tolerant when VDDIO is powered from 2.5 V.
Power
VSS 3, 9, 16 I, Ground Ground reference.
VIN 24 I, Power VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ± 5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO regulator and requires a bypass capacitor to VSS.
When VIN is powered from 1.8 V, for lower power operation, both VIN and VDD_LDO should be connected to 1.8 V supply.
VDDIO 22 I, Power VDDIO powers the LVCMOS IO and 4-level input logic. VDDIO should be connected to 2.5 V ± 5% or 1.8 V ± 5%. VDDIO must always be greater than or equal to VIN. For SMBus access, VDDIO must be 2.5 V ± 5%.
VDD_LDO 23 IO, Power VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to 2.5 V supply. VDD_LDO output requires external 1-µF and 0.1-µF bypass capacitors to VSS. The internal LDO is designed to power internal circuitry only. VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation. When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be connected to the 1.8 V supply.
RSV_L 13 I For pin compatibility with the LMH1219 (11.88 Gbps Ultra-HD adaptive cable equalizer with integrated reclocker), connect RSV_L to a 2.5 V supply with a 0.1-µF bypass capacitor. For low power operation, tie RSV_L to VSS. See Power Supply Recommendations for details.
EP I, Ground EP is the exposed pad at the bottom of the QFN package. The exposed pad must be connected to the ground plane through a via array. See Figure 26 for details.
(1) Note: I = Input, O=Output, IO=Input or Output, OD=Open Drain, LVCMOS=2-State Logic, 4-LEVEL=4-State Logic