SNLS545 Data sheet

SNLS545E March 2017 – July 2022 LMH1297

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RTV|32
- MPQF166B

Thermal pad, mechanical data (Package|Pins)

RTV|32
- QFND101J

Orderable Information

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
PD_{EQ_MODE}	Power dissipation, EQ Mode, Measured with PRBS10, CDR Locked to 11.88 Gbps, VOD = default, HEO/VEO lock monitor disabled	SDI_OUT± disabled OUT0± enabled		275		mW
PD_{EQ_MODE}		SDI_OUT± enabled OUT0± enabled		418		mW
PD_{CD_MODE}	Power dissipation, CD Mode, Measured with PRBS10, CDR Locked to 11.88 Gbps, VOD = default, HEO/VEO lock monitor disabled	SDI_IO± enabled SDI_OUT± disabled OUT0± disabled		305		mW
		SDI_IO± enabled SDI_OUT± disabled OUT0± enabled		350		mW
		SDI_IO± enabled SDI_OUT± enabled OUT0± disabled		442		mW
		SDI_IO± enabled SDI_OUT± enabled OUT0± enabled		485		mW
PD_Z	Power dissipation, Power Save Mode	EQ Mode, Power Save Mode, ENABLE = H, no signal applied at SDI_IO+		25		mW
PD_Z	Power dissipation, Power Save Mode	CD Mode, Power Save Mode, ENABLE = H, no signal applied at IN0±		25		mW
IDD_{EQ_MODE}	Current consumption, EQ Mode, Measured with PRBS10, CDR Locked to 11.88 Gbps, VOD = default, HEO/VEO lock monitor disabled	SDI_OUT± disabled OUT0± enabled		110	137	mA
IDD_{EQ_MODE}		SDI_OUT± enabled OUT0± enabled		167	200	mA
IDD_{CD_MODE}	Current consumption, CD Mode, Measured with PRBS10, CDR Locked to 11.88 Gbps, VOD = default, HEO/VEO lock monitor disabled	SDI_IO± enabled SDI_OUT± disabled OUT0± disabled		122	146	mA
		SDI_IO± enabled SDI_OUT± disabled OUT0± enabled		140	166	mA
		SDI_IO± enabled SDI_OUT± enabled OUT0± disabled		177	211	mA
		SDI_IO± enabled SDI_OUT± enabled OUT0± enabled		194	230	mA
IDD_Z	Current consumption, Power Save Mode	EQ Mode, Power Save Mode, ENABLE = H, no signal applied at SDI_IO+		10		mA
IDD_Z	Current consumption, Power Save Mode	CD Mode, Power Save Mode, ENABLE = H, no signal applied at IN0±		10		mA
IDD_{Z_PD}	Current consumption, Power-Down Mode	EQ Mode, Power-Down Mode, ENABLE = L, no signal applied at SDI_IO+		10	30	mA
IDD_{Z_PD}	Current consumption, Power-Down Mode	CD Mode, Power-Down Mode, ENABLE = L, no signal applied at IN0±		10	30	mA
IDD_{TRANS_EQ}	Current consumption, EQ Mode CDR acquiring lock to 11.88 Gbps, VOD = default, HEO/VEO lock monitor enabled	SDI_OUT± disabled OUT0± enabled			205	mA
IDD_{TRANS_EQ}		SDI_OUT± enabled OUT0± enabled			260	mA
IDD_{TRANS_CD}	Current consumption, CD Mode CDR acquiring lock to 11.88 Gbps, VOD = default, HEO/VEO lock monitor enabled	SDI_IO± enabled SDI_OUT± disabled OUT0± disabled			200	mA
		SDI_IO± enabled SDI_OUT± disabled OUT0± enabled			225	mA
		SDI_IO± enabled SDI_OUT± enabled OUT0± disabled			271	mA
		SDI_IO± enabled SDI_OUT± enabled OUT0± enabled			290	mA
LVCMOS DC SPECIFICATIONS
V_IH	Logic high input voltage	2-level input (SS_N, SCK, MOSI, EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL, ENABLE)	0.72 × VIN		VIN + 0.3	V
V_IH	Logic high input voltage	2-level input (SCL, SDA)	0.7 × VIN		3.6	V
V_IL	Logic low input voltage	2-level input (SS_N, SCK, MOSI, EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL, ENABLE, SCL, SDA)	0		0.3 × VIN	V
V_OH	Logic high output voltage	IOH = –2 mA, (MISO)	0.8 × VIN		VIN	V
V_OL	Logic low output voltage	IOL = 2 mA, (MISO)	0		0.2 × VIN	V
V_OL	Logic low output voltage	IOL = 3 mA, (LOCK_N, SDA)			0.4	V
I_IH	Input high leakage current (Vinput = VIN)	LVCMOS (EQ/CD_SEL, SDI_OUT_SEL, ENABLE)			15	µA
		LVCMOS (OUT0_SEL)			65	µA
		LVCMOS (LOCK_N)			10	µA
		SPI mode: LVCMOS (SS_N, SCK, MOSI)			15	µA
		SMBus mode: LVCMOS (SCL, SDA)			10	µA
I_IL	Input low leakage current (Vinput = GND)	LVCMOS (EQ/CD_SEL, SDI_OUT_SEL, ENABLE)	–50			µA
		LVCMOS (OUT0_SEL)	–15			µA
		LVCMOS (LOCK_N)	–10			µA
		SPI mode: LVCMOS (SCK, MOSI)	–15			µA
		SPI mode: LVCMOS (SS_N)	–50			µA
		SMBus mode: LVCMOS (SCL, SDA)	–10			µA
4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
V_{LVL_H}	LEVEL-H input voltage	Measured voltage at 4-level pin with external 1 kΩ to VIN		VIN		V
V_{LVL_F}	LEVEL-F default voltage	Measured voltage 4-level pin at default		2/3 × VIN		V
V_{LVL_R}	LEVEL-R input voltage	Measured voltage at 4-level pin with external 20 kΩ to VSS		1/3 × VIN		V
V_{LVL_L}	LEVEL-L input voltage	Measured voltage at 4-level pin with external 1 kΩ to VSS		0		V
I_IH	Input high leakage current (Vinput = VIN)	4-levels (HOST_EQ0, MODE_SEL, OUT_CTRL, SDI_VOD)	20	45	80	µA
I_IH	Input high leakage current (Vinput = VIN)	SMBus mode: 4-levels (ADDR0, ADDR1)	20	45	80	µA
I_IL	Input low leakage current (Vinput = GND)	4-levels (HOST_EQ0, MODE_SEL, OUT_CTRL, SDI_VOD)	–160	–93	–40	µA
I_IL	Input low leakage current (Vinput = GND)	SMBus mode: 4-levels (ADDR0, ADDR1)	–160	–93	–40	µA
RECEIVER SPECIFICATIONS (SDI_IO+, EQ MODE)
R_{SDI_IO_TERM}	DC input single-ended termination	SDI_IO+ and SDI_IO– to internal common mode bias	63	75	87	Ω
RL_{SDI_IO_S11}	Input return loss at SDI_IO+ reference to 75 Ω⁽¹⁾	S11, 5 MHz to 1.485 GHz		–30		dB
		S11, 1.485 GHz to 3 GHz		–22		dB
		S11, 3 GHz to 6 GHz		–12		dB
		S11, 6 GHz to 12 GHz		–8		dB
V_{SDI_IO_CM}	SDI_IO+ DC common-mode voltage	Input DC common-mode voltage at SDI_IO+ or SDI_IO- to GND		1.4		V
V_{SDI_IO_WANDER}	Input DC wander	SD, input signal at SDI_IO+, Input launch amplitude = 800 mVp-p		100		mVp-p
V_{SDI_IO_WANDER}	Input DC wander	HD, 3G, 6G, 12G, input signal at SDI_IO+, Input launch amplitude = 800 mVp-p		50		mVp-p
RECEIVER SPECIFICATIONS (IN0±, CD MODE)
R_{IN0_TERM}	DC input differential termination	Measured across IN0+ to IN0–	80	100	120	Ω
RL_{IN0_SDD11}	Input differential return loss⁽¹⁾	SDD11, 10 MHz – 2.8 GHz		–22		dB
		SDD11, 2.8 GHz – 6 GHz		–16		dB
		SDD11, 6 GHz – 11.1 GHz		–10		dB
RL_{IN0_SCD11}	Differential to common-mode input conversion⁽¹⁾	SCD11, 10 MHz to 11.1 GHz		–21		dB
V_{IN0_CM}	DC common-mode voltage	Input common-mode voltage at IN0+ or IN0– to GND		2.06		V
CD_{ON_IN0}	Signal detect (default) Assert ON threshold level for IN0±	11.88 Gbps PRBS10 pattern		20		mVp-p
CD_{OFF_IN0}	Signal detect (default) Deassert OFF threshold level for IN0±	11.88 Gbps PRBS10 pattern		18		mVp-p
DRIVER OUTPUT (SDI_IO+ AND SDI_OUT+, CD MODE)
R_{OUT_TERM}	DC output single-ended termination	SDI_IO+ and SDI_IO–, SDI_OUT+ and SDI_OUT– to VIN	63	75	87	Ω
VOD_{CD_OUTP}	Output single-ended output voltage	Measure AC signal at SDI_IO+ and SDI_OUT+, with SDI_IO– and SDI_OUT– AC terminated with 75 Ω SDI_VOD = H		840		mVp-p
		SDI_VOD = F	720	800	880	mVp-p
		SDI_VOD = R		880		mVp-p
		SDI_VOD = L		760		mVp-p
VOD_{CD_OUTN}	Output single-ended output voltage	Measure AC signal at SDI_IO– and SDI_OUT-, with SDI_IO+ and SDI_OUT+ AC terminated with 75 Ω SDI_VOD = H		840		mVp-p
		SDI_VOD = F	720	800	880	mVp-p
		SDI_VOD = R		880		mVp-p
		SDI_VOD = L		760		mVp-p
PRE_{CD_OUTP}	Output pre-emphasis	Output pre-emphasis boost amplitude at SDI_IO+ and SDI_OUT+, programmed to maximum setting through register, measured at SDI_VOD=F		2		dB
PRE_{CD_OUTN}	Output pre-emphasis	Output pre-emphasis boost amplitude at SDI_IO– and SDI_OUT–, programmed to maximum setting through register, measured at SDI_VOD=F		2		dB
t_{R_F_SDI}	Output rise and fall time⁽¹⁾	Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled 11.88 Gbps		34	42	ps
		5.94 Gbps		36	43	ps
		2.97 Gbps		59	67	ps
		1.485 Gbps		60	73	ps
		270 Mbps	400	550	700	ps
t_{R_F_DELTA}	Output rise and fall time mismatch⁽¹⁾	Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled 11.88 Gbps		3	18	ps
		5.94 Gbps		2.7	12	ps
		2.97 Gbps		0.8	11	ps
		1.485 Gbps		0.8	12	ps
		270 Mbps		72	150	ps
V_OVERSHOOT	Output overshoot or undershoot⁽¹⁾	Measured with PRBS10 pattern, default VOD, default pre-emphasis enabled⁽³⁾ 12G/6G/3G/HD/SD		5%
V_{DC_OFFSET}	DC offset	12G/6G/3G/HD/SD		±0.2		V
V_{DC_WANDER}	DC wander	3G/HD/SD with EQ pathological pattern		20		mV
RL_{CD_S22}	Output return loss at SDI_IO+ and SDI_OUT+ reference to 75 Ω⁽¹⁾	S22, 5 MHz to 1.485 GHz		–25		dB
		S22, 1.485 GHz to 3 GHz		–22		dB
		S22, 3 GHz to 6 GHz		–12		dB
		S22, 6 GHz to 12 GHz		–8		dB
DRIVER OUTPUT (OUT0±, EQ AND CD MODE)
R_{OUT0_TERM}	DC output differential termination	Measured across OUT0+ and OUT0–	80	100	120	Ω
VOD_OUT0	Output differential voltage at OUT0±	Measured with 8T pattern HOST_EQ0 = H		410		mVp-p
		HOST_EQ0 = F	485	560	620	mVp-p
		HOST_EQ0 = R		635		mVp-p
		HOST_EQ0 = L		810		mVp-p
VOD_{OUT0_DE}	De-emphasized output differential voltage at OUT0±	Measured with 8T pattern HOST_EQ0 = H		410		mVp-p
		HOST_EQ0 = F		550		mVp-p
		HOST_EQ0 = R		545		mVp-p
		HOST_EQ0 = L		532		mVp-p
t_R/t_F	Output rise and fall time	Measured with 8T Pattern, 20% – 80% amplitude		45		ps
RL_OUT0-SDD22	Output differential return loss⁽¹⁾	Measured with the device powered up and outputs a 10-MHz clock signal SDD22, 10 MHz – 2.8 GHz		–24		dB
		SDD22, 2.8 GHz – 6 GHz		–16		dB
		SDD22, 6 GHz – 11.1 GHz		–15		dB
RL_OUT0-SCC22	Output common-mode return loss⁽¹⁾	Measured with the device powered up and outputs a 10-MHz clock signal. SCC22, 10 MHz – 4.75 GHz		–12		dB
RL_OUT0-SCC22	Output common-mode return loss⁽¹⁾	SCC22, 4.75 GHz – 11.1 GHz		–9		dB
V_{OUT0_CM}	AC common-mode voltage on OUT0±⁽¹⁾	Default setting, PRBS31, 11.88 Gbps		8		mV (rms)
RECLOCKER OUTPUT JITTER (EQ MODE)
TJ_{EQ_MODE}	Total jitter, reclocked output⁽¹⁾⁽²⁾	Measured at OUT0±, with SDI_OUT disabled (BER ≤ 1E-12), PRBS10, TX launch amplitude = 800 mVp-p before cable to SDI_IO+ 11.88 Gbps: 75-m Belden 1694A		0.14	0.18	UIp-p
		5.94 Gbps: 120-m Belden 1694A		0.1
		2.97 Gbps: 200-m Belden 1694A		0.1
		1.485 Gbps: 300-m Belden 1694A		0.1
		270 Mbps: 600-m Belden 1694A		0.11
TJ_RAW	Total jitter, with CDR bypassed	Measured at OUT0±, with SDI_OUT disabled (BER ≤ 1E-12), PRBS10, TX launch amplitude = 800 mVp-p before cable to SDI_IO+ 125 Mbps: 600-m Belden 1694A		0.2		UIp-p
RECLOCKER OUTPUT JITTER (CD MODE)
AJ_{CD_MODE}	Alignment jitter⁽¹⁾	Measured at SDI_IO+ and SDI_OUT+, OUT0± disabled PRBS10, 3G/HD/SD12G/6G/3G/HD/SD		0.1	0.14	UI
TMJ_{CD_MODE}	Timing jitter⁽¹⁾	Measured at SDI_IO+ and SDI_OUT+, OUT0± disabled PRBS10, 12G/6G/3G/HD/SD		0.45		UI
RECLOCKER SPECIFICATIONS (EQ MODE UNLESS OTHERWISE SPECIFIED)
LOCK_RATE	Reclocker lock data rates	SMPTE 12G, /1		11.88		Gbps
		SMPTE 12G, /1.001		11.868		Gbps
		SMPTE 6G, /1		5.94		Gbps
		SMPTE 6G, /1.001		5.934		Gbps
		SMPTE 3G, /1		2.97		Gbps
		SMPTE 3G, /1.001		2.967		Gbps
		SMPTE HD, /1		1.485		Gbps
		SMPTE HD, /1.001		1.4835		Gbps
		SMPTE SD, /1		270		Mbps
BYPASS_RATE	Reclocker automatically goes to bypass	MADI		125		Mbps
BW_PLL	PLL Bandwidth	Applied 0.2 UI input sinusoidal jitter, measure –3-dB bandwidth on input-to-output jitter transfer 11.88 Gbps		13		MHz
		5.94 Gbps		7		MHz
		2.97 Gbps		5		MHz
		1.485 Gbps		3		MHz
		270 Mbps		1		MHz
J_PEAKING	PLL jitter peaking	11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, 270 Mbps		<0.3		dB
J_{TOL_IN}	SDI_IO+ input jitter tolerance	Sinusoidal jitter tolerance, tested at 3G, 6G and 12G, SJ amplitude swept from 1 MHz to 80 MHz, tested at BER ≤ 1E-12, cable equalizer at SDI_IO+ bypassed		0.65		UI
T_LOCK	Lock time	SMPTE supported data rates, disable HEO/VEO monitor, cable equalizer at SDI_IO+ bypassed		5		ms
T_ADAPT	EQ adapt time at EQ Mode	Adaptation time for cable equalizer at SDI_IO+, reclocker bypassed		5		ms
TEMP_LOCK	VCO temperature lock range	Measured with temperature ramp of 5°C per min, ramp up and down, –40°C to 85°C operating range at 11.88 Gbps		125		°C
TLAT_{EQ_MODE}	Reclocker latency at EQ Mode	Measured from SDI_IO+ to OUT0, 11.88 Gbps, SDI_IO+, 75-m Belden 1694A at SDI_IO+		1.4 UI + 465		ps
TLAT_{EQ_MODE}	Reclocker latency at EQ Mode	Measured from SDI_IO+ to SDI_OUT+, 11.88 Gbps, SDI_IO+, 75-m Belden 1694A at SDI_IO+		1.7 UI + 415		ps
TLAT_{CD_MODE}	Reclocker latency at CD Mode	Measured from IN0± to SDI_IO+, 11.88 Gbps		1.5 UI + 175		ps
TLAT_{CD_MODE}	Reclocker latency at CD Mode	Measured from IN0± to SDI_OUT+, 11.88 Gbps		1.6 UI + 130		ps

(1) This parameter is measured with the LMH1297EVM (Evaluation board for LMH1297).

(2) This limit is ensured by bench characterization and is not production tested.

(3) V_OVERSHOOT overshoot/undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The maximum value specified in Section 7.5 for V_OVERSHOOT is based on bench evaluation across temperature and supply voltages with the LMH1297EVM.