SNLS545E March   2017  – July 2022 LMH1297

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Input Pins and Thresholds
      2. 8.3.2  Equalizer (EQ) and Cable Driver (CD) Mode Control
        1. 8.3.2.1 EQ/CD_SEL Control
        2. 8.3.2.2 OUT0_SEL and SDI_OUT_SEL Control
      3. 8.3.3  Input Carrier Detect
      4. 8.3.4  –6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)
      5. 8.3.5  Continuous Time Linear Equalizer (CTLE)
        1. 8.3.5.1 Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ mode)
        2. 8.3.5.2 Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)
      6. 8.3.6  Clock and Data (CDR) Recovery
      7. 8.3.7  Internal Eye Opening Monitor (EOM)
      8. 8.3.8  Output Function Control
      9. 8.3.9  Output Driver Control
        1. 8.3.9.1 Line-Side Output Cable Driver (SDI_IO+ in CD mode, SDI_OUT+ in EQ or CD mode)
          1. 8.3.9.1.1 Output Amplitude (VOD)
          2. 8.3.9.1.2 Output Pre-Emphasis
          3. 8.3.9.1.3 Output Slew Rate
          4. 8.3.9.1.4 Output Polarity Inversion
        2. 8.3.9.2 Host-Side 100-Ω Output Driver (OUT0± in EQ or CD mode)
      10. 8.3.10 Status Indicators and Interrupts
        1. 8.3.10.1 LOCK_N (Lock Indicator)
        2. 8.3.10.2 CD_N (Carrier Detect)
        3. 8.3.10.3 INT_N (Interrupt)
      11. 8.3.11 Additional Programmability
        1. 8.3.11.1 Cable EQ Index (CEI)
        2. 8.3.11.2 Digital MUTEREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Management Bus (SMBus) Mode
        1. 8.4.1.1 SMBus Read and Write Transaction
          1. 8.4.1.1.1 SMBus Write Operation Format
          2. 8.4.1.1.2 SMBus Read Operation Format
      2. 8.4.2 Serial Peripheral Interface (SPI) Mode
        1. 8.4.2.1 SPI Read and Write Transactions
        2. 8.4.2.2 SPI Write Transaction Format
        3. 8.4.2.3 SPI Read Transaction Format
        4. 8.4.2.4 SPI Daisy Chain
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SMPTE Requirements and Specifications
      2. 9.1.2 Low-Power Optimization in CD Mode
      3. 9.1.3 Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional I/O
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Cable Equalizer With Loop-Through
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stack-Up and Ground References
      2. 11.1.2 High-Speed PCB Trace Routing and Coupling
        1. 11.1.2.1 SDI_IO± and SDI_OUT±:
        2. 11.1.2.2 IN0± and OUT0±:
      3. 11.1.3 Anti-Pads
      4. 11.1.4 BNC Connector Layout and Routing
      5. 11.1.5 Power Supply and Ground Connections
      6. 11.1.6 Footprint Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-D5A8AED3-A3CB-4AA6-B532-B47F5CA0E63A-low.gifFigure 6-1 RTV Package32-Pin QFN(Top View)
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
HIGH-SPEED DIFFERENTIAL I/OS
SDI_IO+ 1 I/O, Analog Single-ended complementary inputs or outputs with on-chip 75-Ω termination at SDI_IO+ and SDI_IO–. SDI_IO± include integrated return loss networks designed to meet the SMPTE input and output return loss requirements. Connect SDI_IO+ to a BNC through a 4.7-µF, AC-coupling capacitor. SDI_IO– should be similarly AC-coupled and terminated with an external 4.7-µF capacitor and 75-Ω resistor to GND.
EQ mode:
SDI_IO+ is the 75-Ω input port of the adaptive cable equalizer for SMPTE video applications.
CD mode:
SDI_IO+ is the 75-Ω output port of the cable driver for SMPTE video applications.
SDI_IO– 2 I/O, Analog
SDI_OUT– 7 O, Analog Single-ended complementary outputs with on-chip 75-Ω termination at SDI_OUT+ and SDI_OUT–. SDI_OUT± include integrated return loss networks designed to meet the SMPTE output return loss requirements. SDI_OUT± is used as a second cable driver. Connect SDI_OUT+ to a BNC through a 4.7-µF, AC-coupling capacitor. SDI_OUT– should be similarly AC-coupled and terminated with an external 4.7-µF capacitor and 75-Ω resistor to GND.
EQ mode:
SDI_OUT± can be enabled as a loop-through 75-Ω output port. It outputs the reclocked data from the adaptive cable equalizer to form a loop-through output with adaptive cable equalizer, reclocker, and cable driver.
CD mode:
SDI_OUT± is the second 75-Ω fan-out cable driver.
SDI_OUT+ 8 O, Analog
IN0– 18 I, Analog Differential inputs from host video processor. On-chip 100-Ω differential termination. Requires external 4.7-µF, AC-coupling capacitors for SMPTE applications.
IN0+ 19 I, Analog
OUT0– 22 O, Analog Differential outputs to host video processor. On-chip 100-Ω differential termination. Requires external 4.7-µF, AC-coupling capacitors for SMPTE applications.
OUT0+ 23 O, Analog
CONTROL PINS
OUT0_SEL 4 I, LVCMOS OUT0_SEL enables the use of the 100-Ω host-side output driver at OUT0±.
See Table 8-3 for details.
OUT0_SEL is internally pulled high by default (OUT0 disabled).
EQ/CD_SEL 5 I, LVCMOS EQ/CD_SEL selects the signal direction of the LMH1297 bidirectional I/O. It configures the LMH1297 as an adaptive equalizer (EQ mode) or as a cable driver (CD mode).
See Table 8-2 for details.
EQ/CD_SEL is internally pulled low by default (EQ mode).
HOST_EQ0 9 I, 4-LEVEL HOST_EQ0 selects the driver output amplitude and de-emphasis level for OUT0± (in EQ mode) and equalizer setting for IN0± (in CD mode).
See Table 8-5 and Table 8-10 for details.
MODE_SEL 12 I, 4-LEVEL MODE_SEL enables the SPI or SMBus serial control interface.
See Table 8-11 for details.
SDI_OUT_SEL 14 I, LVCMOS SDI_OUT_SEL enables the use of the 75-Ω output driver at SDI_OUT±.
See Table 8-3 for details.
SDI_OUT_SEL is internally pulled high by default (SDI_OUT disabled).
OUT_CTRL 17 I, 4-LEVEL OUT_CTRL selects the signal being routed to the output. It is used to enable or bypass the reclocker and to enable or bypass the cable equalizer.
See Table 8-7 for details.
SDI_VOD 24 I, 4-LEVEL SDI_VOD selects one of four output amplitudes for the cable drivers at SDI_IO± and SDI_OUT±.
See Table 8-8 for details.
LOCK_N 27 O, LVCMOS,
OD		 LOCK_N is the reclocker lock indicator. LOCK_N is pulled low when the reclocker has acquired lock condition. LOCK_N is a 3.3-V tolerant, open-drain output. It requires an external resistor to a logic supply.
LOCK_N can be reconfigured to indicate Carrier Detector (CD_N) or Interrupt (INT_N) through register programming. See Section 8.3.10.
ENABLE 32 I, LVCMOS A logic-high at ENABLE enables normal operation for the LMH1297. A logic-low at ENABLE places the LMH1297 in Power-Down mode.
ENABLE is internally pulled high by default.
SPI SERIAL CONTROL INTERFACE, MODE_SEL = F (FLOAT)
SS_N 11 I, LVCMOS SS_N is the Target Select. When SS_N is at logic Low, it enables SPI access to the LMH1297 target device.
SS_N is a 2.5-V LVCMOS input and is internally pulled high by default.
MOSI 13 I, LVCMOS MOSI is the SPI serial control data input to the LMH1297 target device when the SPI bus is enabled. MOSI is a 2.5-V LVCMOS input.
An external pullup resistor is recommended.
MISO 28 O, LVCMOS MISO is the SPI serial control data output from the LMH1297 target device.
MISO is a 2.5-V LVCMOS output.
SCK 29 I, LVCMOS SCK is the SPI serial input clock to the LMH1297 target device when the SPI interface is enabled. SCK is a 2.5-V LVCMOS input.
An external pullup resistor is recommended.
SMBUS SERIAL CONTROL INTERFACE, MODE_SEL = L (1 KΩ TO VSS)
ADDR0 11 Strap, 4-LEVEL ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16 supported SMBus addresses when SMBus is enabled. See Table 8-12 for details.
SDA 13 I/O, LVCMOS,
OD		 SDA is the SMBus bidirectional data line to or from the LMH1297 target device when SMBus is enabled. SDA is an open-drain I/O and requires an external pullup resistor to the SMBus termination voltage. SDA is 3.3-V tolerant.
ADDR1 28 Strap, 4-LEVEL ADDR[1:0] are 4-level straps, read into the device at power up. They are used to select one of the 16 supported SMBus addresses when SMBus is enabled. See Table 8-12 for details.
SCL 29 I/O, LVCMOS,
OD		 SCL is the SMBus input clock to the LMH1297 target device when SMBus is enabled. It is driven by a LVCMOS open-drain driver from the SMBus controller. SCL requires an external pullup resistor to the SMBus termination voltage. SCL is 3.3-V tolerant.
RESERVED
RSV1
RSV2
RSV3
RSV4
RSV5		 10
15
16
25
26		 — Reserved pins. Do not connect.
POWER
VSS 3, 6, 20 I, Ground Ground reference.
VDD_CDR 21 I, Power VDD_CDR powers the reclocker circuitry. It is connected to the same 2.5-V ± 5% supply as VIN.
VIN 30 I, Power VIN is connected to an external 2.5-V ± 5% power supply.
VDD_LDO 31 O, Power VDD_LDO is the output of the internal 1.8-V LDO regulator. VDD_LDO output requires an external 1-µF and 0.1-µF bypass capacitor to VSS. The internal LDO is designed to power internal circuitry only.
EP — I, Ground EP is the exposed pad at the bottom of the RTV package. The exposed pad should be connected to the VSS plane through a 3 × 3 via array.
(1) I = input, O = output, I/O = input or output, OD = open drain, LVCMOS = 2-state logic, 4-LEVEL = 4-state logic