SNLS545E March 2017 – July 2022 LMH1297
PRODUCTION DATA
See Table 9-1 in Bidirectional I/O Design Requirements for general LMH1297 design requirements.
For cable equalizer with loop-through application-specific requirements, reference the guidelines in Table 9-3.
DESIGN PARAMETER | REQUIREMENTS |
---|---|
EQ/CD_SEL Pin | 1 kΩ to VSS (Level L) to enable SDI_IO as a cable EQ input |
OUT0_SEL Pin | 1 kΩ to VSS (Level L) to enable OUT0 as PCB output to the FPGA |
SDI_OUT_SEL Pin | 1 kΩ to VSS (Level L) to enable SDI_OUT as a loop-through output |