SNLS545E March 2017 – July 2022 LMH1297
PRODUCTION DATA
For SPI writes, the R/W bit is 0'b. SPI write transactions are 17 bits per device, and the command is executed on the rising edge of SS_N. The SPI transaction always starts on the rising edge of the clock.
The signal timing for a SPI Write transaction is shown in Figure 7-2. The prime values on MISO (for example, A7') reflect the contents of the shift register from the previous SPI transaction and are do not care for the current transaction.