SBOSA33A September   2021  – December 2021 LMH5485-SP

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: VS+ – VS– = 5 V
    6. 7.6  Electrical Characteristics: VS+ – VS– = 3 V
    7. 7.7  Quality Conformance Inspection
    8. 7.8  Typical Characteristics: 5 V Single Supply
    9. 7.9  Typical Characteristics: 3 V Single Supply
    10. 7.10 Typical Characteristics: 3 V to 5 V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Terminology and Application Assumptions
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tube Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HKX|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics: VS+ – VS– = 3 V

The specifications shown below correspond to the respectively identified subgroup temperature (see Section 7.7), unless otherwise noted. Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a
2-V/V test circuit, and Figure 8-3 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
AC PERFORMANCE
Small-signal bandwidth Vout = 100 mVPP, G = 1 510 MHz
Vout = 100 mVPP, G = 2 475 MHz
Vout = 100 mVPP, G = 5 240 MHz
GBWP Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz
Large-signal bandwidth Vout = 2 VPP 300 MHz
Bandwidth for 0.1-dB flatness Vout = 2 VPP 50 MHz
Slew rate(2) Vout = 2-V step, FPBW 1200 V/µs
Rise/fall time Vout = 2-V step, input ≤ 0.5 ns tr 1.6 ns
Settling time Vout = 2-V step,
tr = 2 ns		 To 1% 5 ns
To 0.1% 9 ns
Overshoot and undershoot Vout = 2-V step, input ≤ 0.3 ns tr 25%
100-kHz harmonic distortion Vout = 2 VPP HD2 –111 dBc
HD3 –150 dBc
10-MHz harmonic distortion Vout = 2 VPP HD2 –80 dBc
HD3 –96 dBc
2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) –89 dBc
3rd-order intermodulation distortion –87 dBc
Input voltage noise f > 100 kHz 2.4 nV/√Hz
Input current noise f > 1 MHz 1.9 pA/√Hz
Overdrive recovery time 2X output overdrive, either polarity 20 ns
Closed-loop output impedance f = 10 MHz (differential) 0.1 Ω
DC PERFORMANCE
AOL Open-loop voltage gain [1, 2, 3] 97 119 dB
Input-referred offset voltage [1, 2, 3] –900 ±100 900 µV
Input offset voltage drift(3) –2.5 ±0.5 2.5 µV/°C
Input bias current Positive out of node [1, 2, 3] 1.7 9 15 µA
Input bias current drift(3) 5 15 nA/°C
Input offset current [1, 2, 3] –650 ±150 650 nA
Input offset current drift(3) –1.5 ±0.3 1.5 nA/°C
INPUT
Common-mode input low < 3-dB degradation in CMRR from midsupply [1, 2, 3] (Vs–) – 0.2 Vs– V
Common-mode input high < 3-dB degradation in CMRR from midsupply [1, 2, 3] (Vs+) – 1.3 (Vs+) –1.2 V
Common-mode rejection ratio Input pins at midsupply [1, 2, 3] 82 100 dB
Input impedance differential mode Input pins at midsupply 110 || 1.25 kΩ || pF
OUTPUT
Output voltage low [1, 2, 3] (Vs–) + 0.2 (Vs–) + 0.25 V
Output voltage high [1, 2, 3] (Vs+) – 0.25 (Vs+) – 0.2 V
Output current drive [1, 2, 3] ±55 ±60 mA
POWER SUPPLY
Specified operating voltage [1, 2, 3] 2.7 3 5.1 V
Quiescent operating current [1, 2, 3] 9 9.7 10.6 mA
±PSRR Power-supply rejection ratio Either supply pin to differential Vout [1, 2, 3] 82 100 dB
POWER DOWN
Enable voltage threshold [1, 2, 3] (Vs–) + 1.7 V
Disable voltage threshold [1, 2, 3] (Vs–) + 0.7 V
Disable pin bias current PD = Vs– → Vs+ [1, 2, 3] 20 50 nA
Power-down quiescent current PD = (Vs–) + 0.7 V [1, 2, 3] 2 30 µA
PD = Vs– [1, 2, 3] 1 8 µA
Turnon-time delay Time from PD = low to
Vout = 90% of final value		 100 ns
Turnoff time delay Time from PD = low to
Vout = 10% of final value		 60 ns
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidth Vocm = 100 mVPP 140 MHz
Slew rate(2) Vocm = 1-V step 350 V/µs
Gain [1, 2, 3] 0.975 0.987 0.990 V/V
Input bias current Considered positive out of node [1, 2, 3] –0.7 0.1 0.7 µA
Input impedance Vocm input driven to midsupply 47 || 1.2 kΩ || pF
Default voltage offset from midsupply Vocm pin open [1, 2, 3] –45 ±10 45 mV
CM Vos Common-mode offset voltage Vocm input driven to midsupply [1, 2, 3] –8 ±2 8 mV
CM VOS drift(3) Vocm input driven to midsupply –20 ±4 20 mV/°C
Common-mode loop supply headroom to negative supply < ±15-mV shift from midsupply CM Vos [1, 2, 3] 0.94 V
Common-mode loop supply headroom to positive supply < ±15-mV shift from midsupply CM Vos [1, 2, 3] 1.2 V
(1) For subgroup definitions, please see Section 7.7
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB.
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
(4) Specifications are from input Vocm pin to differential output average voltage.