SNOSAL8D April   2006  – September 2021 LMH6321

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Operating Ratings
    3. 5.3 Thermal Information
    4. 5.4 ±15 V Electrical Characteristics
    5. 5.5 ±5 V Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6Application Hints
    1. 6.1  Buffers
    2. 6.2  Supply Bypassing
    3. 6.3  Load Impedence
    4. 6.4  Source Inductance
    5. 6.5  Overvoltage Protection
    6. 6.6  Bandwidth and Stability
    7. 6.7  Output Current and Short Circuit Protection
    8. 6.8  Thermal Management
      1. 6.8.1 Heatsinking
      2. 6.8.2 Determining Copper Area
      3. 6.8.3 Procedure
      4. 6.8.4 Example
    9. 6.9  Error Flag Operation
    10. 6.10 Single Supply Operation
    11. 6.11 Slew Rate
  7. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KTW|7
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Error Flag Operation

The LMH6321 provides an open collector output at the EF pin that produces a low voltage when the Thermal Shutdown Protection is engaged, due to a fault condition. Under normal operation, the Error Flag pin is pulled up to V+ by an external resistor. When a fault occurs, the EF pin drops to a low voltage and then returns to V+ when the fault disappears. This voltage change can be used as a diagnostic signal to alert a microprocessor of a system fault condition. If the function is not used, the EF pin can be either tied to ground or left open. If this function is used, a 10 kΩ, or larger, pull-up resistor (R2 in Figure 6-2) is recommended. The larger the resistor the lower the voltage will be at this pin under thermal shutdown. Table 6-3 shows some typical values of VEF for 10 kΩ and 100 kΩ.

Table 6-3 VEF vs. R2
R2 (inFigure 6-2)At V+ = 5 VAt V+ = 15 V
10 kΩ0.24 V0.55 V
100 KΩ0.036 V0.072 V