SNOSAL8D April   2006  – September 2021 LMH6321

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Operating Ratings
    3. 5.3 Thermal Information
    4. 5.4 ±15 V Electrical Characteristics
    5. 5.5 ±5 V Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6Application Hints
    1. 6.1  Buffers
    2. 6.2  Supply Bypassing
    3. 6.3  Load Impedence
    4. 6.4  Source Inductance
    5. 6.5  Overvoltage Protection
    6. 6.6  Bandwidth and Stability
    7. 6.7  Output Current and Short Circuit Protection
    8. 6.8  Thermal Management
      1. 6.8.1 Heatsinking
      2. 6.8.2 Determining Copper Area
      3. 6.8.3 Procedure
      4. 6.8.4 Example
    9. 6.9  Error Flag Operation
    10. 6.10 Single Supply Operation
    11. 6.11 Slew Rate
  7. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KTW|7
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Bandwidth and Stability

As can be seen in the schematic of Figure 6-2, a small capacitor is inserted in parallel with the series input resistors. The reason for this is to compensate for the natural band-limiting effect of the 1st order filter formed by this resistor and the input capacitance of the buffer. With a typical CIN of 3.5 pF (Figure 6-2), a pole is created at

Equation 1. fp2 = 1/(2πR1CIN) = 4.5 MHz

This will band-limit the buffer and produce further phase lag. If used in an op amp-loop application with an amplifier that has the same order of magnitude of unity gain crossing as fp2, this additional phase lag will produce oscillation.

The solution is to add a small feed-forward capacitor (phase lead) around the input resistor, as shown in Figure 6-2. The value of this capacitor is not critical but should be such that the time constant formed by it and the input resistor that it is in parallel with (RIN) be at least five times the time constant of RINCIN. Therefore,

Equation 2. C1 = (5RIN/R1)(CIN)

from Section 5.4, RIN is 250 kΩ.

In the case of the example in Figure 6-2, RINCIN produces a time-constant of 870 ns, so C1 should be chosen to be a minimum of 4.4 μs, or 438 pF. The value of C1 (1000 pF) shown in Figure 6-2 gives 10 μs.