SNAS579G March 2012 – December 2014 LMK00105
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Refer to Clock Inputs to properly interface the 3.3-V LVCMOS oscillator output to the CLKin input buffer of the LMK00105.
See Figure 9 for output termination schemes depending on the receiver application. Since the CPU/FPGA inputs and PLL input require different input voltage levels, the LMK00105 output banks are supplied from separate Vddo rails of 3.3 V and 1.8 V for CLKout0/1 (Bank A) and CLKout2 (Bank B), respectively.
Unused outputs can be left floating.
See Power Supply Recommendations for recommended power supply filtering and decoupling/bypass techniques.