SNAS512J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision I (December 2017) to Revision J (May 2023)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added the Device Functional Modes, Application Information, Typical Application, and Layout sectionsGo
  • Added Frequency Range for LVPECL, LVDS, HCSL and LVCMOS in Features section.Go
  • Added PCIe 5.0 and 6.0 to Applications Go
  • Added LMK00301A in Package Information Table.Go
  • Added PCIe 5.0 and PCIe 6.0 additive jitter specifications in Electrical Characteristics.Go
  • Changed HCSL Maximum Output Frequency Range to 800 MHz Electrical Characteristics.Go
  • Added test conditions for HCSL Duty Cycle and ΔVCROSS in Electrical Characteristics.Go
  • Updated typical plots for HCSL, LVDS and LVPECL Phase Noise at 100 MHz in Typical Characteristics section. Go
  • Added typical plots for HCSL Output Swing (VOD) vs Frequency in Typical Characteristics section.Go
  • Moved Clock Input and Clock Outputs to Device Functional Modes section.Go
  • Added application use case in Application Information Go
  • Added PCI Express Application example in Typical Application section.Go
  • Added Driving the Clock Input and Crystal Interface topics in Design Requirement section.Go
  • Moved Termination and Use of Clock Drivers in Detailed Design Procedure section.Go
  • Added HCSL Phase Noise plot in Application Performance Plots section.Go
  • Added layout guidelines in Layout Guidelines section.Go
  • Added PCB layout example for LMK00301 in Layout Example section.Go

Changes from Revision H (March 2016) to Revision I (December 2017)

  • Added and updated info to the following sections: Applications; Description; Electrical Characteristics: Current Consumption; Electrical Characteristics: HCSL Outputs; and Power Supply Sequencing Go
  • Added LMK00301A orderableGo
  • Added PCIe 4.0 to Applications Go
  • Included difference between LMK00301 and LMK00301A to Description Go
  • Added Device Comparison Table Go
  • Added data for Icc and Icco of LMK00301A LVDS Driver in Electrical Characteristics: Current Consumption Go
  • Added PCIe 4.0 Additive Jitter Spec in Electrical Characteristics: HCSL Outputs Go
  • Added note about specs for LMK00301 and LMK00301A in footnote (2) of Electrical Characteristics Go
  • Added short paragraph about LMK00301A in Power Supply Sequencing Go

Changes from Revision G (May 2013) to Revision H (March 2016)

  • Added "Ultra-Low Additive Jitter" to document title Go
  • Added, updated, or renamed the following sections: Specifications; Detailed Description; Application and Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
  • Changed Cin (typ) from 1 pF to 4 pF (based on updated test method) in Electrical Characteristics: Crystal Interface. Go
  • Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVPECL Outputs Go
  • Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVDS Outputs Go
  • Added footnote for VI_SE parameter in the Electrical Characteristics table.Go
  • Added new paragraph at end of Driving the Clock Inputs Go
  • Changed Cin = 4 pF (typ, based on updated test method) in Crystal Interface Go
  • Added POWER SUPPLY SEQUENCINGGo

Changes from Revision F (February 2013) to Revision G (May 2013)

  • Changed Target Applications by adding additional applications to the second and third bullets, and removing High-Speed and Serial Interfaces from first bullet.Go
  • Changed guarantee to ensure.Go
  • Changed guarantee to ensure in Elec Char condition.Go
  • Changed VCM text to condition for VIH to VCM parametersGo
  • Deleted VIH min value from Electrical Characteristics Table.Go
  • Deleted VIL max value from Electrical Characteristics table.Go
  • Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table.Go
  • Changed guarantee to ensure.Go
  • Changed "guarantee" to "ensure" throughout datasheet.Go
  • Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in Electrical Characteristics Table.Go
  • Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
  • Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
  • Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to Differential LVDS Operation with AC Coupling to Receivers Go
  • Changed graphic for Differential LVDS Operation, AC Coupling, No Biasing by the Receiver and updated caption.Go