SNAS512J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2.2 Power Dissipation Example #2: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical Characteristics are used.

  • Maximum VCC = VCCO = 3.465 V. Maximum ICC and ICCO values
  • CLKin0/CLKin0* input is selected
  • Banks A and B are configured for LVPECL: all outputs terminated with 50 Ω to VT = VCCO – 2 V
  • REFout is enabled with 5-pF load
  • TA = 85°C

Using the maximum supply current and power calculations from the previous section, we can compute PTOTAL and PDEVICE.

  • From Equation 6: ICC_TOTAL = 10.5 mA + 27 mA + 27 mA + 5.5 mA = 70 mA
  • From ICCO_PECL max spec: ICCO_BANK_A = ICCO_BANK_B = 197 mA
  • From Equation 8: PTOTAL = 3.465 V × (70 mA + 197 mA + 197 mA + 10 mA) = 1642.4 mW
  • From Equation 9: PRT_PECL = ((2.57 V – 1.47 V)2/50 Ω) + ((1.72 V – 1.47 V)2/50 Ω) = 25.5 mW (per output pair)
  • From Equation 10: PVTT_PECL = 1.47 V × [ ((2.57 V – 1.47 V) / 50 Ω) + ((1.72 V – 1.47 V) / 50 Ω) ] = 39.5 mW (per output pair)
  • From Equation 11: PRT_HCSL = 0 mW (no HCSL outputs)
  • From Equation 12: PDEVICE = 1642.4 mW – (10 × (25.5 mW + 39.5 mW)) – 0 mW = 992.4 mW

In this worst-case example, the IC device will dissipate about 992.4 mW or 60% of the total power (1642.4 mW), while the remaining 40% will be dissipated in the LVPECL emitter resistors (255 mW for 10 pairs) and termination voltage (395 mW into VCCO – 2 V).

Based on θJA of 28.5°C/W, the estimated die junction temperature would be about 28.3°C above ambient, or 113.3 °C when TA = 85°C.