SNAS577G February   2012  – August 2018 LMK00304

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      LVPECL Output Swing (VOD) vs. Frequency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
  9. 9 Application and Implementation
    1. 9.1 Driving the Clock Inputs
    2. 9.2 Crystal Interface
    3. 9.3 Termination and Use of Clock Drivers
      1. 9.3.1 Termination for DC-Coupled Differential Operation
      2. 9.3.2 Termination for AC-Coupled Differential Operation
      3. 9.3.3 Termination for Single-Ended Operation
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Current Consumption and Power Dissipation Calculations
      1. 10.2.1 Power Dissipation Example: Worst-Case Dissipation
    3. 10.3 Power Supply Bypassing
      1. 10.3.1 Power Supply Ripple Rejection
    4. 10.4 Thermal Management
      1. 10.4.1 Support for PCB Temperature up to 105°C
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from F Revision (March 2016) to G Revision

  • Added new rows to the Thermal Information tableGo
  • Added the Support for PCB Temperature up to 105°C section Go

Changes from E Revision (May 2013) to F Revision

  • Added "Ultra-Low Additive Jitter" to document titleGo
  • Added, updated, or renamed the following sections: Specifications; Detailed Description; Application and Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
  • Changed Cin (typ) from 1 pF to 4 pF (based on updated test method) in Electrical Characteristics: Crystal InterfaceGo
  • Added "Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVPECL Outputs Go
  • Added "Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVDS Outputs Go
  • Added footnote for VI_SE parameter in the Electrical Characteristics table. Go
  • Added new paragraph at end of Driving the Clock InputsGo
  • Changed "LMK00301" to "LMK00304" in Figure 27 and Figure 28Go
  • Changed Cin = 4 pF (typ, based on updated test method) in Crystal InterfaceGo
  • Added POWER SUPPLY SEQUENCING Go

Changes from D Revision (February 2013) to E Revision

  • Changed VCM text to condition for VIH to VCM parameter group.Go
  • Deleted VIH min value from Electrical Characteristics table.Go
  • Deleted VIL max value from Electrical Characteristics table.Go
  • Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table.Go
  • Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in Electrical Characteristics Table.Go
  • Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
  • Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
  • Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to Differential LVDS Operation with AC Coupling to Receivers.Go
  • Changed graphic for Differential LVDS Operation, AC Coupling, No Biasing by the Receiver and updated caption.Go