10.1 Power Supply Sequencing

When powering the Vcc and Vcco pins from separate supply rails, it is recommended for the supplies to reach their regulation point at approximately the same time while ramping up, or reach ground potential at the same time while ramping down. Using simultaneous or ratiometric power supply sequencing prevents internal current flow from Vcc to Vcco pins that could occur when Vcc is powered before Vcco.

10.2 Current Consumption and Power Dissipation Calculations

The current consumption values specified in Electrical Characteristics can be used to calculate the total power dissipation and IC power dissipation for any device configuration. The total V_CC core supply current (I_{CC_TOTAL}) can be calculated using Equation 5:

Since the output supplies (V_CCOA, V_CCOB, V_CCOC) can be powered from 3 independent voltages, the respective output supply currents (I_{CCO_BANK_A}, I_{CCO_BANK_B}, and I_{CCO_CMOS}) should be calculated separately.

I_{CCO_BANK} for either Bank A or B can be directly taken from the corresponding output supply current spec (I_{CCO_PECL}, I_{CCO_LVDS}, or I_{CCO_HCSL}) provided the output loading matches the specified conditions. Otherwise, I_{CCO_BANK} should be calculated as follows:

Table 6 shows the typical I_{BANK_BIAS} values and I_{OUT_LOAD} expressions for LVPECL, LVDS, and HCSL.

For LVPECL, it is possible to use a larger termination resistor (R_T) to ground instead of terminating with 50 Ω to V_TT = Vcco - 2 V; this technique is commonly used to eliminate the extra termination voltage supply (V_TT) and potentially reduce device power dissipation at the expense of lower output swing. For example, when Vcco is 3.3 V, a R_T value of 160 Ω to ground will eliminate the 1.3 V termination supply without sacrificing much output swing. In this case, the typical I_{OUT_LOAD} is 25 mA, so I_{CCO_PECL} for a fully-loaded bank reduces to 95 mA (vs. 100 mA with 50 Ω resistors to Vcco – 2 V).

Once the current consumption is known for each supply, the total power dissipation (P_TOTAL) can be calculated as:

If the device is configured with LVPECL or HCSL outputs, then it is also necessary to calculate the power dissipated in any termination resistors (P_{RT_ PECL} and P_{RT_HCSL}) and in any LVPECL termination voltages (P_{VTT_PECL}). The external power dissipation values can be calculated as follows:

Finally, the IC power dissipation (P_DEVICE) can be computed by subtracting the external power dissipation values from P_TOTAL as follows:

10.3 Power Supply Bypassing

The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF, placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the device between the supply and ground planes. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance.

10.3.1 Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00306, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc).

For the LMK00306, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vcco supply. The PSRR test setup is shown in Figure 39.

Figure 39. PSRR Test Setup

A signal generator was used to inject a sinusoidal signal onto the Vcco supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the Vcco pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz under the following power supply ripple conditions:

• Ripple amplitude: 100 mVpp on Vcco = 2.5 V
• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

Equation 12. DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_CLK)] * 10¹²

The “PSRR vs. Ripple Frequency” plots in Typical Characteristics show the ripple-induced phase spur levels for the differential output types at 156.25 MHz and 312.5 MHz . The LMK00306 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range for all differential output types. The phase spur levels for LVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using Equation 12, these phase spur levels translate to Deterministic Jitter values of 2.57 ps pk-pk at 156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for Vcco = 3.3 V under the same ripple amplitude and frequency conditions.

10.4 Thermal Management

Power dissipation in the LMK00306 device can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, T_A (ambient temperature) plus device power dissipation times R_θJA should not exceed 125 °C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 40. More information on soldering WQFN packages can be obtained at: http://www.ti.com/packaging.

Figure 40. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 40 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated.