SNAS578 Data sheet

SNAS578D February 2012 – March 2016 LMK00306

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

NJK|36

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_CC, V_CCO	Supply Voltages	-0.3	3.6	V
V_IN	Input Voltage	-0.3	(V_CC + 0.3)	V
T_STG	Storage Temperature	-65	+150	°C
T_L	Lead Temperature (solder 4 s)		+260	°C
T_J	Junction Temperature		+150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
		Machine model (MM)	±150
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

6.3 Recommended Operating Conditions

	PARAMETER	MIN	TYP	MAX	UNIT
T_A	Ambient Temperature Range	-40	25	85	°C
T_J	Junction Temperature			125	°C
V_CC	Core Supply Voltage Range	3.15	3.3	3.45	V
V_CCO	Output Supply Voltage Range ⁽¹⁾⁽²⁾	3.3 – 5% 2.5 – 5%	3.3 2.5	3.3 + 5% 2.5 + 5%	V

(1) The output supply voltages or pins (V_CCOA, V_CCOB, and V_CCOC) will be called V_CCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.

(2) Vcco should be less than or equal to Vcc (Vcco ≤ Vcc).

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		NJK0036A (WQFN)	UNIT
THERMAL METRIC⁽¹⁾⁽²⁾		36 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	31.8	°C/W
R_{θJC(top) (DAP)}	Junction-to-case (top) thermal resistance	7.2	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Specification assumes 9 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the package. It is recommended that the maximum number of vias be used in the board layout.

6.5 Electrical Characteristics

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. ⁽¹⁾⁽¹⁾

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION⁽²⁾
I_{CC_CORE}	Core Supply Current, All Outputs Disabled	CLKinX selected			8.5	10.5	mA
I_{CC_CORE}	Core Supply Current, All Outputs Disabled	OSCin selected			10	13.5	mA
I_{CC_PECL}	Additive Core Supply Current, Per LVPECL Bank Enabled				20	26.5	mA
I_{CC_LVDS}	Additive Core Supply Current, Per LVDS Bank Enabled				24	29.5	mA
I_{CC_HCSL}	Additive Core Supply Current, Per HCSL Bank Enabled				29	35	mA
I_{CC_CMOS}	Additive Core Supply Current, LVCMOS Output Enabled				3.5	5.5	mA
I_{CCO_PECL}	Additive Output Supply Current, Per LVPECL Bank Enabled	Includes Output Bank Bias and Load Currents, R_T = 50 Ω to Vcco - 2V on all outputs in bank			100	123	mA
I_{CCO_LVDS}	Additive Output Supply Current, Per LVDS Bank Enabled				20	27.5	mA
I_{CCO_HCSL}	Additive Output Supply Current, Per HCSL Bank Enabled	Includes Output Bank Bias and Load Currents, R_T = 50 Ω on all outputs in bank			50	65	mA
I_{CCO_CMOS}	Additive Output Supply Current, LVCMOS Output Enabled	200 MHz, C_L = 5 pF	Vcco = 3.3 V ± 5%		9	10	mA
I_{CCO_CMOS}	Additive Output Supply Current, LVCMOS Output Enabled	200 MHz, C_L = 5 pF	Vcco = 2.5 V ± 5%		7	8	mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRR_PECL	Ripple-Induced Phase Spur Level Differential LVPECL Output⁽³⁾	100 kHz, 100 mVpp Ripple Injected on Vcco, Vcco = 2.5 V	156.25 MHz		-65		dBc
PSRR_PECL			312.5 MHz		-63		dBc
PSRR_LVDS	Ripple-Induced Phase Spur Level Differential LVDS Output⁽³⁾		156.25 MHz		-76		dBc
PSRR_LVDS	Ripple-Induced Phase Spur Level Differential LVDS Output⁽³⁾		312.5 MHz		-74		dBc
PSRR_HCSL	Ripple-Induced Phase Spur Level Differential HCSL Output⁽³⁾		156.25 MHz		-72		dBc
PSRR_HCSL	Ripple-Induced Phase Spur Level Differential HCSL Output⁽³⁾		312.5 MHz		-63		dBc
CMOS CONTROL INPUTS (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)
V_IH	High-Level Input Voltage			1.6		Vcc	V
V_IL	Low-Level Input Voltage			GND		0.4	V
I_IH	High-Level Input Current	V_IH = Vcc, Internal pull-down resistor				50	µA
I_IL	Low-Level Input Current	V_IL = 0 V, Internal pull-down resistor		-5	0.1		µA
*CLOCK INPUTS (CLKin0/CLKin0, CLKin1/CLKin1)*
f_CLKin	Input Frequency Range⁽¹⁰⁾	Functional up to 3.1 GHz Output frequency range and timing specified per output type (refer to LVPECL, LVDS, HCSL, LVCMOS output specifications)		DC		3.1	GHz
V_IHD	Differential Input High Voltage	CLKin driven differentially				Vcc	V
V_ILD	Differential Input Low Voltage			GND			V
V_ID	Differential Input Voltage Swing⁽⁴⁾			0.15		1.3	V
V_CMD	Differential Input Common Mode Voltage	V_ID = 150 mV		0.25		Vcc - 1.2	V
		V_ID = 350 mV		0.25		Vcc - 1.1
		V_ID = 800 mV		0.25		Vcc -0.9
V_IH	Single-Ended Input High Voltage	CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within V_CM range				Vcc	V
V_IL	Single-Ended Input Low Voltage			GND			V
V_{I_SE}	Single-Ended Input Voltage Swing⁽¹⁵⁾⁽¹⁷⁾			0.3		2	Vpp
V_CM	Single-Ended Input Common Mode Voltage			0.25		Vcc - 1.2	V
ISO_MUX	Mux Isolation, CLKin0 to CLKin1	f_OFFSET > 50 kHz, P_CLKinX = 0 dBm	f_CLKin0 = 100 MHz		-84		dBc
			f_CLKin0 = 200 MHz		-82
			f_CLKin0 = 500 MHz		-71
			f_CLKin0 = 1000 MHz		-65
CRYSTAL INTERFACE (OSCin, OSCout)
F_CLK	External Clock Frequency Range⁽¹⁰⁾	OSCin driven single-ended, OSCout floating				250	MHz
F_XTAL	Crystal Frequency Range	Fundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)⁽⁵⁾		10		40	MHz
C_IN	OSCin Input Capacitance				4		pF
*LVPECL OUTPUTS (CLKoutAn/CLKoutAn, CLKoutBn/CLKoutBn)*
f_{CLKout_FS}	Maximum Output Frequency Full V_OD Swing⁽¹⁰⁾⁽¹¹⁾	V_OD ≥ 600 mV, R_L = 100 Ω differential	Vcco = 3.3 V ± 5%, R_T = 160 Ω to GND	1.0	1.2		GHz
f_{CLKout_FS}	Maximum Output Frequency Full V_OD Swing⁽¹⁰⁾⁽¹¹⁾	V_OD ≥ 600 mV, R_L = 100 Ω differential	Vcco = 2.5 V ± 5%, R_T = 91 Ω to GND	0.75	1.0		GHz
f_{CLKout_RS}	Maximum Output Frequency Reduced V_OD Swing⁽¹⁰⁾⁽¹¹⁾	V_OD ≥ 400 mV, R_L = 100 Ω differential	Vcco = 3.3 V ± 5%, R_T = 160 Ω to GND	1.5	3.1		GHz
f_{CLKout_RS}	Maximum Output Frequency Reduced V_OD Swing⁽¹⁰⁾⁽¹¹⁾	V_OD ≥ 400 mV, R_L = 100 Ω differential	Vcco = 2.5 V ± 5%, R_T = 91 Ω to GND	1.5	2.3		GHz
Jitter_ADD	Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz⁽¹⁰⁾⁽⁶⁾⁽¹⁶⁾	Vcco = 2.5 V ± 5%: R_T = 91 Ω to GND, Vcco = 3.3 V ± 5%: R_T = 160 Ω to GND, R_L = 100 Ω differential	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		77	98	fs
Jitter_ADD			CLKin: 156.25 MHz, Slew rate ≥ 3 V/ns		54	78	fs
Jitter_ADD	Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz⁽⁶⁾	Vcco = 3.3 V, R_T = 160 Ω to GND, R_L = 100 Ω differential	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		59		fs
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		64
			CLKin: 625 MHz, Slew rate ≥ 3 V/ns		30
Jitter_ADD	Additive RMS Jitter with LVPECL clock source from LMK03806⁽⁶⁾⁽⁷⁾	Vcco = 3.3 V, R_T = 160 Ω to GND, R_L = 100 Ω differential	CLKin: 156.25 MHz, J_SOURCE = 190 fs RMS (10 kHz to 1 MHz)		20		fs
Jitter_ADD		Vcco = 3.3 V, R_T = 160 Ω to GND, R_L = 100 Ω differential	CLKin: 156.25 MHz, J_SOURCE = 195 fs RMS (12 kHz to 20 MHz)		51		fs
Noise Floor	Noise Floor f_OFFSET ≥ 10 MHz⁽⁸⁾⁽⁹⁾	Vcco = 3.3 V, R_T = 160 Ω to GND, R_L = 100 Ω differential	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		-162.5		dBc/Hz
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		-158.1
			CLKin: 625 MHz, Slew rate ≥ 3 V/ns		-154.4
DUTY	Duty Cycle⁽¹⁰⁾	50% input clock duty cycle		45%		55%
V_OH	Output High Voltage	T_A = 25 °C, DC Measurement, R_T = 50 Ω to Vcco - 2 V		Vcco - 1.2	Vcco - 0.9	Vcco - 0.7	V
V_OL	Output Low Voltage			Vcco - 2.0	Vcco - 1.75	Vcco - 1.5	V
V_OD	Output Voltage Swing⁽⁴⁾			600	830	1000	mV
V_OD	Output Voltage Swing⁽⁴⁾			600	830	1000	mV
t_R	Output Rise Time 20% to 80%⁽¹⁵⁾	R_T = 160 Ω to GND, Uniform transmission line up to 10 in. with 50-Ω characteristic impedance, R_L = 100 Ω differential,C_L ≤ 5 pF			175	300	ps
t_F	Output Fall Time 80% to 20%⁽¹⁵⁾				175	300	ps
*LVDS OUTPUTS (CLKoutAn/CLKoutAn, CLKoutBn/CLKoutBn)*
f_{CLKout_FS}	Maximum Output Frequency Full V_OD Swing⁽¹⁰⁾⁽¹¹⁾	V_OD ≥ 250 mV, R_L = 100 Ω differential		1.0	1.6		GHz
f_{CLKout_RS}	Maximum Output Frequency Reduced V_OD Swing⁽¹⁰⁾⁽¹¹⁾	V_OD ≥ 200 mV, R_L = 100 Ω differential		1.5	2.1		GHz
Jitter_ADD	Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz⁽¹⁰⁾⁽⁶⁾⁽¹⁶⁾	R_L = 100 Ω differential	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		94	115	fs
Jitter_ADD		R_L = 100 Ω differential	CLKin: 156.25 MHz, Slew rate ≥ 3 V/ns		70	90	fs
Jitter_ADD	Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz⁽⁶⁾	Vcco = 3.3 V, R_L = 100 Ω differential	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		89		fs
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		77
			CLKin: 625 MHz, Slew rate ≥ 3 V/ns		37
Noise Floor	Noise Floor f_OFFSET ≥ 10 MHz⁽⁸⁾⁽⁹⁾	Vcco = 3.3 V, R_L = 100 Ω differential	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		-159.5		dBc/Hz
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		-157.0
			CLKin: 625 MHz, Slew rate ≥ 3 V/ns		-152.7
DUTY	Duty Cycle⁽¹⁰⁾	50% input clock duty cycle		45%		55%
V_OD	Output Voltage Swing⁽⁴⁾	T_A = 25 °C, DC Measurement, R_L = 100 Ω differential		250	400	450	mV
ΔV_OD	Change in Magnitude of V_OD for Complementary Output States			-50		50	mV
V_OS	Output Offset Voltage			1.125	1.25	1.375	V
ΔV_OS	Change in Magnitude of V_OS for Complementary Output States			-35		35	mV
I_SA I_SB	Output Short Circuit Current Single Ended	T_A = 25 °C, Single ended outputs shorted to GND		-24		24	mA
I_SAB	Output Short Circuit Current Differential	Complementary outputs tied together		-12		12	mA
t_R	Output Rise Time 20% to 80%⁽¹⁵⁾	Uniform transmission line up to 10 inches with 50-Ω characteristic impedance, R_L = 100 Ω differential, C_L ≤ 5 pF			175	300	ps
t_F	Output Fall Time 80% to 20%⁽¹⁵⁾				175	300	ps
*HCSL OUTPUTS (CLKoutAn/CLKoutAn, CLKoutBn/CLKoutBn)*
f_CLKout	Output Frequency Range⁽¹⁰⁾	R_L = 50 Ω to GND, C_L ≤ 5 pF		DC		400	MHz
Jitter_{ADD_PCIe}	Additive RMS Phase Jitter for PCIe 3.0⁽¹⁰⁾	PCIe Gen 3, PLL BW = 2–5 MHz, CDR = 10 MHz	CLKin: 100 MHz, Slew rate ≥ 0.6 V/ns		0.03	0.15	ps
Jitter_ADD	Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz⁽⁶⁾	Vcco = 3.3 V, R_T = 50 Ω to GND	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		77		fs
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		86
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		86
Noise Floor	Noise Floor f_OFFSET ≥ 10 MHz⁽⁸⁾⁽⁹⁾	Vcco = 3.3 V, R_T = 50 Ω to GND	CLKin: 100 MHz, Slew rate ≥ 3 V/ns		-161.3		dBc/Hz
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		-156.3
			CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns		-156.3
DUTY	Duty Cycle⁽¹⁰⁾	50% input clock duty cycle		45%		55%
V_OH	Output High Voltage	T_A = 25 °C, DC Measurement, R_T = 50 Ω to GND		520	810	920	mV
V_OL	Output Low Voltage	T_A = 25 °C, DC Measurement, R_T = 50 Ω to GND		-150	0.5	150	mV
V_CROSS	Absolute Crossing Voltage⁽¹⁰⁾⁽¹²⁾	R_L = 50 Ω to GND, C_L ≤ 5 pF		160	350	460	mV
ΔV_CROSS	Total Variation of V_CROSS⁽¹⁰⁾⁽¹²⁾	R_L = 50 Ω to GND, C_L ≤ 5 pF				140	mV
t_R	Output Rise Time 20% to 80%⁽¹⁵⁾⁽¹²⁾	250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance, R_L = 50 Ω to GND, C_L ≤ 5 pF			300	500	ps
t_F	Output Fall Time 80% to 20%⁽¹⁵⁾⁽¹²⁾				300	500	ps
LVCMOS OUTPUT (REFout)
f_CLKout	Output Frequency Range⁽¹⁰⁾	C_L ≤ 5 pF		DC		250	MHz
Jitter_ADD	Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz⁽⁶⁾	Vcco = 3.3 V, C_L ≤ 5 pF	100 MHz, Input Slew rate ≥ 3 V/ns		95		fs
Noise Floor	Noise Floor f_OFFSET ≥ 10 MHz⁽⁸⁾⁽⁹⁾	Vcco = 3.3 V, C_L ≤ 5 pF	100 MHz, Input Slew rate ≥ 3 V/ns		-159.3		dBc/Hz
DUTY	Duty Cycle⁽¹⁰⁾	50% input clock duty cycle		45%		55%
V_OH	Output High Voltage	1 mA load		Vcco - 0.1			V
V_OL	Output Low Voltage	1 mA load				0.1	V
I_OH	Output High Current (Source)	Vo = Vcco / 2	Vcco = 3.3 V		28		mA
I_OH	Output High Current (Source)		Vcco = 2.5 V		20		mA
I_OL	Output Low Current (Sink)		Vcco = 3.3 V		28		mA
I_OL	Output Low Current (Sink)		Vcco = 2.5 V		20		mA
t_R	Output Rise Time 20% to 80%⁽¹⁵⁾⁽¹²⁾	250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance, R_L = 50 Ω to GND, C_L ≤ 5 pF			225	400	ps
t_F	Output Fall Time 80% to 20%⁽¹⁵⁾⁽¹²⁾				225	400	ps
t_EN	Output Enable Time⁽¹³⁾	C_L ≤ 5 pF				3	cycles
t_DIS	Output Disable Time⁽¹³⁾	C_L ≤ 5 pF				3	cycles
PROPAGATION DELAY and OUTPUT SKEW
t_{PD_PECL}	Propagation Delay CLKin-to-LVPECL⁽¹⁵⁾	R_T = 160 Ω to GND, R_L = 100 Ω differential, C_L ≤ 5 pF		180	360	540	ps
t_{PD_LVDS}	Propagation Delay CLKin-to-LVDS⁽¹⁵⁾	R_L = 100 Ω differential, CL ≤ 5 pF		200	400	600	ps
t_{PD_HCSL}	Propagation Delay CLKin-to-HCSL⁽¹⁵⁾⁽¹²⁾	R_T = 50 Ω to GND, C_L ≤ 5 pF		295	590	885	ps
t_{PD_CMOS}	Propagation Delay CLKin-to-LVCMOS⁽¹⁵⁾⁽¹²⁾	C_L ≤ 5 pF	Vcco = 3.3 V	900	1475	2300	ps
t_{PD_CMOS}	Propagation Delay CLKin-to-LVCMOS⁽¹⁵⁾⁽¹²⁾	C_L ≤ 5 pF	Vcco = 2.5 V	1000	1550	2700	ps
t_SK(O)	Output Skew LVPECL/LVDS/HCSL ⁽¹⁰⁾⁽¹²⁾⁽¹⁴⁾	Skew specified between any two CLKouts with the same buffer type. Load conditions per output type are the same as propagation delay specifications.			30	50	ps
t_SK(PP)	Part-to-Part Output Skew LVPECL/LVDS/HCSL ⁽¹⁵⁾⁽¹²⁾⁽¹⁴⁾				80	120	ps

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.

(2) See Power Supply Recommendations for more information on current consumption and power dissipation calculations.

(3) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10^{(PSRR / 20)}) / (π * f_CLK) ] * 1E12

(4) See Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.

(5) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations.

(6) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD = SQRT(J_OUT² - J_SOURCE²), where J_OUT is the total RMS jitter measured at the output driver and J_SOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: J_ADD = SQRT(2*10^dBc/10) / (2*π*f_CLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log₁₀(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Characteristics.

(7) 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). J_SOURCE = 190 fs RMS (10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information.

(8) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(9) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.

(10) Specification is ensured by characterization and is not tested in production.

(11) See Typical Characteristics for output operation over frequency.

(12) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(13) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.

(14) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.

(15) Parameter is specified by design, not tested in production.

(16) 100 MHz and 156.25 MHz input source from Rohde & Schwarz SMA100A Low-Noise Signal Generator and Sine-to-Square-wave Conversion block.

(17) For clock input frequency ≥ 100 MHz, CLKinX can be driven with single-ended (LVCMOS) input swing up to 3.3 Vpp. For clock input frequency < 100 MHz, the single-ended input swing should be limited to 2 Vpp max to prevent input saturation (refer to Driving the Clock Inputs for interfacing 2.5 V/3.3 V LVCMOS clock input < 100 MHz to CLKinX).

6.6 Typical Characteristics

Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, T_A = 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Consult Table 1 at the end of Typical Characteristics for graph footnotes.

Figure 1. LVPECL Output Swing (V_OD) vs. Frequency

Figure 3. LVPECL Output Swing @ 156.25 MHz

Figure 5. LVPECL Output Swing @ 1.5 GHz

Figure 7. HCSL Output Swing @ 250 MHz

Figure 9. Noise Floor vs. CLKin Slew Rate @ 100 MHz

Figure 11. Noise Floor vs. CLKin Slew Rate @ 625 MHz

See Note 1 in Graph Notes

Figure 13. RMS Jitter vs. CLKin Slew Rate @ 156.25 MHz

Figure 15. PSRR vs. Ripple Frequency @ 156.25 MHz

Figure 17. Propagation Delay vs. Temperature

See Note 1 in Graph Notes table

Figure 19. LVDS Phase Noise @ 100 MHz

See Notes 2 and 3 in Graph Notes table

Figure 21. Crystal Power Dissipation vs. R_LIM

Figure 2. LVDS Output Swing (V_OD) vs. Frequency

Figure 4. LVDS Output Swing @ 156.25 MHz

Figure 6. LVDS Output Swing @ 1.5 GHz

Figure 8. LVCMOS Output Swing @ 250 MHz

Figure 10. Noise Floor vs. CLKin Slew Rate @ 156.25 MHz

See Note 1 in Graph Notes

Figure 12. RMS Jitter vs. CLKin Slew Rate @ 100 MHz

Figure 14. RMS Jitter vs. CLKin Slew Rate @ 625 MHz

Figure 16. PSRR vs. Ripple Frequency @ 312.5 MHz

See Note 1 in Graph Notes table

Figure 18. LVPECL Phase Noise @ 100 MHz

See Note 1 in Graph Notes table

Figure 20. HCSL Phase Noise @ 100 MHz

See Notes 2 and 3 in Graph Notes table.

Figure 22. LVDS Phase Noise in Crystal Mode

Table 1. Graph Notes

NOTE
(1)	The typical RMS jitter values in the plots show the total output RMS jitter (J_OUT) for each output buffer type and the source clock RMS jitter (J_SOURCE). From these values, the Additive RMS Jitter can be calculated as: J_ADD = SQRT(J_OUT² - J_SOURCE²).
(2)	20 MHz crystal characteristics: Abracon ABL series, AT cut, C_L = 18 pF , C₀ = 4.4 pF measured (7 pF max), ESR = 8.5 Ω measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).
(3)	40 MHz crystal characteristics: Abracon ABLS2 series, AT cut, C_L = 18 pF , C₀ = 5 pF measured (7 pF max), ESR = 5 Ω measured (40 Ω max), and Drive Level = 1 mW max (100 µW typical).