SNAS636C December   2013  – July 2021 LMK00338

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Power Supply Recommendations
    1. 9.1 Current Consumption and Power Dissipation Calculations
      1. 9.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 9.2 Power Supply Bypassing
      1. 9.2.1 Power Supply Ripple Rejection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision B (June 2017) to Revision C (July 2021)

  • Changed data sheet title from: LMK00338 8-Output Differential Clock Buffer and Level Translator to: LMK00338 8-Output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Clock Buffer and Level Translator Go
  • Changed Target Applications by adding additional applications to the second and third bullets, and removing High-Speed and Serial Interfaces from first bullet.Go
  • Added PCIe Gen5 to the data sheetGo
  • Changed guarantee to ensure throughout.Go
  • Added PCIe 4.0 compliance dataGo
  • Added additive RMS phase jitter for PCIe 4.0 and PCIe 5.0 to the Electrical Characteristics tableGo
  • Removed the LVPECL Phase Noise at 100 MHz graph Go
  • Changed the third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in the Electrical Characteristics tableGo
  • Changed the bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
  • Changed the Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go

Changes from Revision A (October 2014) to Revision B (June 2017)

  • Changed CLKoutA_EN and CLKoutB_EN pins to CLKoutA_EN and CLKoutB_EN throughout the data sheet Go

Changes from Revision * (December 2013) to Revision A (October 2014)

  • Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
  • Added PCIE Gen4 additive jitter to the Electrical Characteristics table Go
  • Changed 1 MHz to 12 kHz Go
  • Added Figure 10-1 Go