SNAS522K September   2011  – December 2023 LMK03806

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Features Description
      1. 7.3.1 Serial MICROWIRE Timing Diagram and Terminology
      2. 7.3.2 Crystal Support With Buffered Outputs
      3. 7.3.3 Integrated Loop Filter Poles
      4. 7.3.4 Integrated VCO
      5. 7.3.5 Clock Distribution
        1. 7.3.5.1 CLKout DIvider
        2. 7.3.5.2 Programmable Output Type
        3. 7.3.5.3 Clock Output Synchronization
      6. 7.3.6 Default Start-Up Clocks
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 General Information
        1. 7.5.1.1 Special Programming Case for R0 to R5 for CLKoutX_Y_DIV > 25
        2. 7.5.1.2 Recommended Initial Programming Sequence
        3. 7.5.1.3 READBACK
          1. 7.5.1.3.1 Readback Example
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Crystal Interface
      2. 8.1.2 Driving OSCin Pins With a Single-Ended Source
      3. 8.1.3 Driving OSCin Pins With a Differential Source
      4. 8.1.4 Frequency Planning With the LMK03806
      5. 8.1.5 Configuring the PLL
        1. 8.1.5.1 Example PLL Configuration
      6. 8.1.6 Digital Lock Detect
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
          1. 8.2.2.1.1 Clock Architect
          2. 8.2.2.1.2 Clock Design Tool
          3. 8.2.2.1.3 Calculation Using LCM
        2. 8.2.2.2 Device Configuration
        3. 8.2.2.3 PLL Loop Filter Design
          1. 8.2.2.3.1 Example Loop Filter Design
        4. 8.2.2.4 Other Device Specific Configuration
          1. 8.2.2.4.1 Digital Lock Detect
        5. 8.2.2.5 Device Programming
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 System Level Diagram
    4. 8.4 Best Design Practices
      1. 8.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 8.4.2 LVPECL Outputs
      3. 8.4.3 Sharing MICROWIRE (SPI) Lines
      4. 8.4.4 SYNC Pin
      5. 8.4.5 CLKout Vcc Pins
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Current Consumption and Power Dissipation Calculations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Register Maps
    1. 10.1  Default Device Register Settings After Power On Reset
    2. 10.2  Register R0 TO R5
      1. 10.2.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
      2. 10.2.2 RESET
      3. 10.2.3 POWERDOWN
      4. 10.2.4 CLKoutX_Y_DIV, Clock Output Divide
    3. 10.3  Registers R6 TO R8
      1. 10.3.1 CLKoutX_TYPE
    4. 10.4  REGISTER R9
    5. 10.5  REGISTER R10
      1. 10.5.1 OSCout1_TYPE, LVPECL Output Amplitude Control
      2. 10.5.2 OSCout0_TYPE
      3. 10.5.3 EN_OSCoutX, OSCout Output Enable
      4. 10.5.4 OSCoutX_MUX, Clock Output Mux
      5. 10.5.5 OSCout_DIV, Oscillator Output Divide
    6. 10.6  REGISTER R11
      1. 10.6.1 NO_SYNC_CLKoutX_Y
      2. 10.6.2 SYNC_POL_INV
      3. 10.6.3 SYNC_TYPE
      4. 10.6.4 EN_PLL_XTAL
    7. 10.7  REGISTER R12
      1. 10.7.1 LD_MUX
      2. 10.7.2 LD_TYPE
      3. 10.7.3 SYNC_PLL_DLD
    8. 10.8  REGISTER R13
      1. 10.8.1 READBACK_TYPE
      2. 10.8.2 GPout0
    9. 10.9  REGISTER 14
      1. 10.9.1 GPout1
    10. 10.10 REGISTER 16
    11. 10.11 REGISTER 24
      1. 10.11.1 PLL_C4_LF, PLL Integrated Loop Filter Component
      2. 10.11.2 PLL_C3_LF, PLL Integrated Loop Filter Component
      3. 10.11.3 PLL_R4_LF, PLL Integrated Loop Filter Component
      4. 10.11.4 PLL_R3_LF, PLL Integrated Loop Filter Component
    12. 10.12 REGISTER 26
      1. 10.12.1 EN_PLL_REF_2X, PLL Reference Frequency Doubler
      2. 10.12.2 PLL_CP_GAIN, PLL Charge Pump Current
      3. 10.12.3 PLL_DLD_CNT
    13. 10.13 REGISTER 28
      1. 10.13.1 PLL_R, PLL R Divider
    14. 10.14 REGISTER 29
      1. 10.14.1 OSCin_FREQ, PLL Oscillator Input Frequency Register
      2. 10.14.2 PLL_N_CAL, PLL N Calibration Divider
    15. 10.15 REGISTER 30
      1. 10.15.1 PLL_P, PLL N Prescaler Divider
      2. 10.15.2 PLL_N, PLL N Divider
    16. 10.16 REGISTER 31
      1. 10.16.1 READBACK_ADDR
      2. 10.16.2 uWire_LOCK
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C, Junction Temperature TJ ≤ 125°C.
Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C, at Recommended Operating ConditionsRecommended Operating Conditions at the time of product characterization and are not ensured.(3)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CURRENT CONSUMPTION
ICC_PDPowerdown supply currentNo DC path to ground on OSCout1/1*(1)1mA
ICC_CLKSSupply current with all clocks enabled(2)CLKoutX_Y_DIV = 16,
CLKoutX_TYPE = 1 (LVDS),
PLL locked		445mA
EXTERNAL CLOCK (OSCin) SPECIFICATIONS
fOSCinPLL reference Input(4)1500MHz
SLEWOSCinPLL reference clock minimum slew rate on OSCin(9)20% to 80%0.150.5V/ns
VOSCinInput voltage for OSCin or OSCin*(9)AC coupled; Single-ended (Unused pin AC coupled to GND)0.22.4Vpp
VIDOSCinDifferential voltage swingAC coupled, see Figure 6-10.21.55|V|
VSSOSCin0.43.1Vpp
VOSCin-offsetDC offset voltage between OSCin/OSCin*
OSCinX* - OSCinX		Each pin AC coupled20mV
fdoubler_maxDoubler input frequency(9)EN_PLL_REF_2X = 1;
OSCin Duty Cycle 40% to 60%		155MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
fXTALCrystal frequency range(9)RESR ≤ 40 Ω
CL ≤ 20 pF		1620.5MHz
RESR ≤ 80 Ω
CL ≤ 22 pF		616MHz
PXTALCrystal power dissipationVectron VXB1 crystal, 20.48 MHz, RESR ≤ 40 Ω
CL ≤ 20 pF		120µW
CINInput capacitance of the OSCin port–40°C to +85°C6pF
RMS JITTER PERFORMANCE
XO mode(14)(15)(16)Integration bandwidth
10 kHz to 1 MHz		156.25 MHz, LVDS/LVPECL81fs
312.5 MHz, LVDS/LVPECL85fs
Integration bandwidth
12 kHz to 20 MHz		100 MHz, LVDS139fs
100 MHz, LVPECL117fs
106.25 MHz, LVDS145fs
106.25 MHz, LVPECL126fs
156.25 MHz, LVDS111fs
156.25 MHz, LVPECL100fs
312.5 MHz, LVDS108fs
312.5 MHz, LVPECL95fs
622.08 MHz, LVDS/LVPECL141fs
Integration bandwidth
637 kHz to 10 MHz		106.25 MHz, LVDS78fs
106.25 MHz, LVPECL60fs
Integration bandwidth
1.875 MHz to 20 MHz		156.25 MHz, LVDS70fs
156.25 MHz, LVPECL57fs
312.5 MHz, LVDS57fs
312.5 MHz, LVPECL43fs
Crystal mode jitter(10)(11)(12)Integration bandwidth
10 kHz to 1 MHz		156.25 MHz, LVDS/LVPECL190fs
312.5 MHz, LVDS/LVPECL200fs
Integration bandwidth
12 kHz to 20 MHz		100 MHz, LVDS235fs
100 MHz, LVPECL210fs
106.25 MHz, LVDS280fs
106.25 MHz, LVPECL250fs
156.25 MHz, LVDS200fs
156.25 MHz, LVPECL195fs
312.5 MHz, LVDS220fs
312.5 MHz, LVPECL190fs
622.08 MHz, LVDS/LVPECL255fs
Integration bandwidth
637 kHz to 10 MHz		106.25 MHz, LVDS90fs
106.25 MHz, LVPECL65fs
Integration bandwidth
1.875 MHz to 20 MHz		156.25 MHz, LVDS75fs
156.25 MHz, LVPECL65fs
312.5 MHz, LVDS60fs
312.5 MHz, LVPECL45fs
PHASE NOISE PERFORMANCE
XO mode phase noise100 MHz (LVDS/LVPECL)(14)10 kHz–142dBc/Hz
100 kHz–143dBc/Hz
1 MHz–157dBc/Hz
10 MHz (LVDS)–159dBc/Hz
20 MHz (LVDS)–160dBc/Hz
10 MHz (LVPECL)–160dBc/Hz
20 MHz (LVPECL)–161dBc/Hz
106.25 MHz (LVDS/LVPECL)(15)10 kHz–141dBc/Hz
100 kHz–140dBc/Hz
1 MHz–156dBc/Hz
10 MHz (LVDS)–159dBc/Hz
20 MHz (LVDS)–160dBc/Hz
10 MHz (LVPECL)–162dBc/Hz
20 MHz (LVPECL)–163dBc/Hz
156.25 MHz (LVDS/LVPECL)(14)10 kHz–139dBc/Hz
100 kHz–140dBc/Hz
1 MHz–153dBc/Hz
10 MHz (LVDS)–159dBc/Hz
20 MHz (LVDS)–159dBc/Hz
10 MHz (LVPECL)–160dBc/Hz
20 MHz (LVPECL)–160dBc/Hz
312.5 MHz (LVDS/LVPECL)(14)10 kHz–132dBc/Hz
100 kHz–133dBc/Hz
1 MHz–148dBc/Hz
10 MHz (LVDS)–154dBc/Hz
20 MHz (LVDS)–155dBc/Hz
10 MHz (LVPECL)–157dBc/Hz
20 MHz (LVPECL)–158dBc/Hz
622.08 MHz (LVDS/LVPECL)(16)10 kHz–123dBc/Hz
100 kHz–121dBc/Hz
1 MHz–143dBc/Hz
10 MHz (LVDS)–154dBc/Hz
20 MHz (LVDS)–154dBc/Hz
10 MHz (LVPECL)–157dBc/Hz
20 MHz (LVPECL)–158dBc/Hz
Crystal mode phase noise100 MHz (LVDS/LVPECL)(10)10 kHz–129dBc/Hz
100 kHz–137dBc/Hz
1 MHz–156dBc/Hz
10 MHz (LVDS)–158dBc/Hz
20 MHz (LVDS)–159dBc/Hz
10 MHz (LVPECL)–160dBc/Hz
20 MHz (LVPECL)–161dBc/Hz
106.25 MHz (LVDS/LVPECL)(11)10 kHz–124dBc/Hz
100 kHz–137dBc/Hz
1 MHz–156dBc/Hz
10 MHz (LVDS)–158dBc/Hz
20 MHz (LVDS)–159dBc/Hz
10 MHz (LVPECL)–160dBc/Hz
20 MHz (LVPECL)–161dBc/Hz
156.25 MHz (LVDS/LVPECL)(10)10 kHz–125dBc/Hz
100 kHz–132dBc/Hz
1 MHz–153dBc/Hz
10 MHz (LVDS)–158dBc/Hz
20 MHz (LVDS)–159dBc/Hz
10 MHz (LVPECL)–160dBc/Hz
20 MHz (LVPECL)–160dBc/Hz
312.5 MHz (LVDS/LVPECL)(10)10 kHz–119dBc/Hz
100 kHz–126dBc/Hz
1 MHz–147dBc/Hz
10 MHz (LVDS)–153dBc/Hz
20 MHz (LVDS)–154dBc/Hz
10 MHz (LVPECL)–156dBc/Hz
20 MHz (LVPECL)–157dBc/Hz
622.08 MHz (LVDS/LVPECL)(12)10 kHz–110dBc/Hz
100 kHz–120dBc/Hz
1 MHz–140dBc/Hz
10 MHz (LVDS)–153dBc/Hz
20 MHz (LVDS)–153dBc/Hz
10 MHz (LVPECL)–154dBc/Hz
20 MHz (LVPECL)–154dBc/Hz
PLL PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS
fPDPhase detector frequency155MHz
ICPoutSOURCEPLL charge pump source currentVCPout=VCC/2, PLL_CP_GAIN = 0100µA
VCPout=VCC/2, PLL_CP_GAIN = 1400µA
VCPout=VCC/2, PLL_CP_GAIN = 21600µA
VCPout=VCC/2, PLL_CP_GAIN = 33200µA
ICPoutSINKPLL charge pump sink currentVCPout=VCC/2, PLL_CP_GAIN = 0–100µA
VCPout=VCC/2, PLL_CP_GAIN = 1–400µA
VCPout=VCC/2, PLL_CP_GAIN = 2–1600µA
VCPout=VCC/2, PLL_CP_GAIN = 3–3200µA
ICPout%MISCharge pump sink/source mismatchVCPout=VCC/2, TA = 25°C3%10%
ICPoutVTUNEMagnitude of charge pump current vs. charge pump voltage variation0.5 V < VCPout < VCC – 0.5 V
TA = 25°C		4%
ICPout%TEMPCharge pump current vs. temperature variation4%
ICPoutTRICharge pump leakage0.5 V < VCPout < VCC – 0.5 V10nA
PN10kHzPLL 1/f noise at 10 kHz offset(5). Normalized to
1-GHz output frequency		PLL_CP_GAIN = 400 µA–118dBc/Hz
PLL_CP_GAIN = 3200 µA–121dBc/Hz
PN1HzNormalized phase noise contribution(6)PLL_CP_GAIN = 400 µA–222.5dBc/Hz
PLL_CP_GAIN = 3200 µA–227dBc/Hz
L(f)PLL phase noise
(Assumes a very wide bandwidth, noiseless crystal, 2500-MHz output frequency, and 25-MHz phase detector frequency)		1-kHz Offset–93dBc/Hz
10 kHz–103dBc/Hz
100-kHz Offset–116dBc/Hz
1-MHz Offset–116dBc/Hz
INTERNAL VCO SPECIFICATIONS
fVCOVCO tuning range23702600MHz
KVCOFine tuning sensitivity
(The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range).		fVCO at low end16MHz/V
fVCO at high end21
|ΔTCL|Allowable temperature drift for continuous lock(7) (9)After programming R30 for lock, no changes to output configuration are permitted to guarantee continuous lock125°C
L(f)Phase noise
(Assumes a very narrow loop bandwidth)		10-kHz Offset–87dBc/Hz
100-kHz Offset–112dBc/Hz
1-MHz Offset–133dBc/Hz
CLOCK SKEW
|TSKEW|Maximum CLKoutX to CLKoutY(8) (9)LVDS-to-LVDS, T = 25°C,
fCLK = 800 MHz, RL= 100 Ω
AC coupled		30ps
LVPECL-to-LVPECL,
T = 25°C,
fCLK = 800 MHz, RL= 100 Ω
emitter resistors =
240 Ω to GND
AC coupled		30ps
Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout(8) (9)RL = 50 Ω, CL = 5 pF,
T = 25°C, FCLK = 100 MHz.(8)		100ps
MixedSKEWLVDS or LVPECL to LVCMOSSame device, T = 25°C,
250 MHz		750ps
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1
fCLKoutOperating frequency(9) (13)RL = 100 Ω1300MHz
VODDifferential output voltageFigure 6-2T = 25°C, DC measurement
AC-coupled to receiver input
R = 100-Ω differential termination		250400450|mV|
VSS500800900mVpp
ΔVODChange in magnitude of VOD for complementary output states–5050mV
VOSOutput offset voltage1.1251.251.375V
ΔVOSChange in VOS for complementary output states35|mV|
TR / TFOutput rise time20% to 80%, RL = 100 Ω200ps
Output fall time80% to 20%, RL = 100 Ω200ps
ISA
ISB		Output short circuit current - single-endedSingle-ended output shorted to GND, T = 25°C–2424mA
ISABOutput short circuit current - differentialComplimentary outputs tied together, T = 25°C–1212mA
LVPECL CLOCK OUTPUTS (CLKoutX)
fCLKoutOperating frequency(9) (13)1300MHz
TR / TF20% to 80% output riseRL = 100 Ω, emitter resistors = 240 Ω to GND
CLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)		150ps
80% to 20% output fall time
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2
VOHOutput high voltageT = 25°C, DC measurement
Termination = 50 Ω to
VCC – 1.4 V		VCC – 1.03V
VOLOutput low voltageVCC – 1.41V
VODOutput voltageFigure 6-2305380440|mV|
VSS610760880mVpp
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3
VOHOutput high voltageT = 25°C, DC measurement
Termination = 50 Ω to
VCC – 1.7 V		VCC – 1.07V
VOLOutput low voltageVCC – 1.69V
VODOutput voltageFigure 6-2545625705|mV|
VSS109012501410mVpp
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4
VOHOutput high voltageT = 25°C, DC Measurement
Termination = 50 Ω to
VCC – 2 V		VCC – 1.10V
VOLOutput low voltageVCC – 1.97V
VODOutput voltageFigure 6-2660870965|mV|
VSS132017401930mVpp
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5
VOHOutput high voltageT = 25°C, DC Measurement
Termination = 50 Ω to
VCC – 2.3 V		VCC – 1.13V
VOLOutput low voltageVCC – 2.20V
VODOutput voltageFigure 6-280010701200|mV|
VSS160021402400mVpp
LVCMOS CLOCK OUTPUTS (CLKoutX)
fCLKoutOperating frequency(9)5-pF Load250MHz
VOHOutput high voltage1-mA LoadVCC – 0.1V
VOLOutput low voltage1-mA Load0.1V
IOHOutput high current (Source)VCC = 3.3 V, VO = 1.65 V28mA
IOLOutput low current (Sink)VCC = 3.3 V, VO = 1.65 V28mA
DUTYCLKOutput duty cycle(9)VCC/2 to VCC/2, FCLK = 100 MHz, T = 25°C455055%
TROutput rise time20% to 80%, RL = 50 Ω,
CL = 5 pF		400ps
TFOutput fall time80% to 20%, RL = 50 Ω,
CL = 5 pF		400ps
DIGITAL OUTPUTS (Ftest/LD, Readback, GPoutX)
VOHHigh-level output voltageIOH = –500 µAVCC – 0.4V
VOLLow-level output voltageIOL = 500 µA0.4V
DIGITAL INPUTS (SYNC)
VIHHigh-level input voltage1.6VCCV
VILLow-level input voltage0.4V
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)
VIHHigh-level input voltage1.6VCCV
VILLow-level input voltage0.4V
IIHHigh-level input currentVIH = VCC525µA
IILLow-level input currentVIL = 0–55µA
(1) If emitter resistors are placed on the OSCout1/1* pins, there will be a DC current to ground which will cause powerdown Icc to increase.
(2) Load conditions for output clocks: LVDS: 100 Ω differential. See Current Consumption and Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.
(3) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
(4) FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.
(5) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
(6) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPD). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPD is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(7) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40°C to 85°C without violating specifications.
(8) Equal loading and identical clock output configuration on each clock output is required for specification to be valid.
(9) Guaranteed by characterization.
(10) Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values are C1 = 220 pF, C2 = 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 20 MHz the loop bandwidth = 62 kHz and phase margin = 76°.
(11) Jitter and phase noise data for 106.25 MHz collected using an ECS crystal, part number ECS-200-20-30B-DU. Loop filter values are C1 = 220 pF, C2 = 18 nF, R2 = 820 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 32 kHz and phase margin = 69°.
(12) Jitter and phase noise data for 622.08 MHz collected using a Vectron crystal, part number VXB1-1137-15M360. Loop filter values are C1 = 100 pF, C2 = 120 nF, R2 = 470 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 54 kHz and phase margin = 86°.
(13) Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.
(14) Jitter and phase noise data for 100 MHz, 156.25, and 312.5 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values are C1 = 39 pF, C2 = 3.3 nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler disabled. VCO frequency = 2500 MHz using a phase detector frequency = 100 MHz the loop bandwidth = 80 kHz and phase margin = 60°.
(15) Jitter and phase noise data for 106.25 MHz collected using a Wenzel crystal oscillator, part number 501–04623G. Loop filter values are C1 = 39pF, C2 = 3.3 nF, R2 = 820Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler disabled. VCO frequency = 2550 MHz using a phase detector frequency = 10 MHz the loop bandwidth = 80 kHz and phase margin = 60°.
(16) Jitter and phase noise data for 622.08 MHz collected using a Crystec oscillator, part number CVHD-950. Loop filter values are C1 = 39 pF, C2 = 3.3 nF, R2 = 680 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω. Charge pump current = 3.2 mA. LVPECL emitter resistors, Re = 240 Ω. Reference doubler enabled. VCO frequency = 2488.32 MHz using a phase detector frequency = 30.72 MHz the loop bandwidth = 80 kHz and phase margin = 60°.