SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32 (even and odd) with 50% output duty cycle, using duty cycle correction mode. The output of this divider may also be directed to SDCLKoutY, where Y = X + 1.