SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
Using the PLLatinum Sim configuration, the TICS Pro software is manually updated with this information to meet the required application. For the JESD204B outputs, place the device clocks on the DCLKoutX output, then turn on the paired SDCLKoutY output for SYSREF output. For non-JESD204B outputs, both DCLKoutX and paired SDCLKoutY may be driven by the device clock divider to maximize number of available outputs.
Frequency planning for assignment of outputs:
In this example, the 245.76-MHz ADC output requires the best performance. DCLKout2 on the LMK0482x provides the best noise floor / performance. The 245.76 MHz is placed on DCLKout2 with 10.24-MHz SYSREF on SDCLKout3.
In this example, the 983.04-MHz DAC output is placed on DCLKout4 and DCLKout6, with 10.24-MHz SYSREF on paired SDCLKout5 and SDCLKout7 outputs.
In this example, the 122.88-MHz FPGA JESD204B output is placed on DCLKout10, with 10.24-MHz SYSREF on paired SDCLKout11 output.
Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on DCLKout8 and SDCLKout9.
The register programming can be validated live on the device, with a SPI header wired to a TI USB2ANY programmer. When the device programming is completed as desired in the TICS Pro software, it is possible to export the register settings by using the Export Hex Registers option in the file menu.