SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL at the phase detector. When the time error(phase error) between the two signals is less than a specified window size (ε), a lock detect count increments. When the lock detect count reaches a user-specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted (true). When digital lock detect is true, a single phase comparison outside the specified window causes digital lock detect to be deasserted (false). This is illustrated in Figure 17 .
This incremental lock detect count feature functions as a digital filter, to ensure that lock detect is not asserted when the phases of R and N are within the specified tolerance for a brief time during initial phase lock.
See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.
The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.
The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting Holdover for more info.
NOTE
In cases where the period of the phase detector frequency approaches the value of the default PLL1_WND_SIZE increment (40 ns), the lock detect circuit will not function with the default value of PLL1_WND_SIZE. For PLL1 phase detector frequencies at or above 25 MHz, TI recommends setting PLL1_WND_SIZE less than or equal to 0x02 (19 ns).