SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
This register contains the delay value for PLL1 N and R delays.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7:6 | NA | 0 | Reserved | |
5:3 | PLL1_R_DLY | 0 | Increasing delay of PLL1_R_DLY causes the outputs to lag from CLKinX. For use in zero-delay mode. | |
Field Value | Gain | |||
0 (0x00) | 0 ps | |||
1 (0x01) | 205 ps | |||
2 (0x02) | 410 ps | |||
3 (0x03) | 615 ps | |||
4 (0x04) | 820 ps | |||
5 (0x05) | 1025 ps | |||
6 (0x06) | 1230 ps | |||
7 (0x07) | 1435 ps | |||
2:0 | PLL1_N_DLY | 0 | Increasing delay of PLL1_N_DLY causes the outputs to lead from CLKinX. For use in zero-delay mode. | |
Field Value | Gain | |||
0 (0x00) | 0 ps | |||
1 (0x01) | 205 ps | |||
2 (0x02) | 410 ps | |||
3 (0x03) | 615 ps | |||
4 (0x04) | 820 ps | |||
5 (0x05) | 1025 ps | |||
6 (0x06) | 1230 ps | |||
7 (0x07) | 1435 ps |