SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
tds | Setup time for SDI edge to SCLK rising edge | See Figure 1 | 10 | ns | ||
tdH | Hold time for SDI edge from SCLK rising edge | See Figure 1 | 10 | ns | ||
tSCLK | Period of SCLK | See Figure 1 | 50(21) | ns | ||
tHIGH | High width of SCLK | See Figure 1 | 25 | ns | ||
tLOW | Low width of SCLK | See Figure 1 | 25 | ns | ||
tcs | Setup time for CS* falling edge to SCLK rising edge | See Figure 1 | 10 | ns | ||
tcH | Hold time for CS* rising edge from SCLK rising edge | See Figure 1 | 30 | ns | ||
tdv | SCLK falling edge to valid read back data | See Figure 1 | 20 | ns |
Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete, the CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming.
4-wire mode read back has same timing as the SDIO pin.
R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.
W1 and W0 are written as 0.