SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
The global SYSREF divider includes a digital delay block, which allows a global phase shift with respect to the other clocks.
Each local SYSREF clock output includes both an analog and additional local digital delay, for unique phase adjustment of each SYSREF clock.
The local analog delay allows for 150-ps steps.
The local digital delay and SYSREF_HS bit allows the each individual SYSREF output to be delayed from, 1.5 to 11 VCO cycles. The delay step can be as small as half the period of the clock distribution path, by using the DCLKoutX_HS bit. For example, a 2-GHz VCO frequency results in 250 ps coarse tuning steps.