SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
To ensure proper JESD204B operation, the timing relationship between the SYSREF and the device clock must be adjusted for optimum setup and hold time as shown in . The global SYSREF digital delay (SYSREF_DDLY). local SYSREF digital delay (SDCLKoutY_DDLY), local SYSREF half step (SDCLKoutY_HS), and local SYSREF analog delay (SDCLKoutY_ADLY, SDCLKoutY_ADLY_EN) can be adjusted to provide the required setup and hold time between SYSREF and device clock. It is also possible to adjust the device clock digital delay (DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL), device clock half step (DCLKoutX_HS), device clock analog delay (DCLKoutX_ADLY, DCLKoutX_ADLY_EN), and device clock muxes (DCLKoutX_MUX, DCLKoutX_ADLY_MUX) to adjust phase with respect to SYSREF.
Depending on the settings for DCLKoutX and the SYSREF divider, some adjustment may be needed to correctly align DCLKoutX to SDCLKoutY. Equation 1 and Equation 2 predict the relative DCLKoutX to SDCLKoutY delay:
where
For the relative delay equations, the cycle delay rather than the register value should be used, since cycle delay does not always equal register value (example: _CNTH/_CNTL=0, delay=16). Device clock duty cycle correction can be enabled for both digital and analog paths, either by setting DCLKoutX_MUX=1 (digital only), or by setting DCLKoutX_MUX=3 and DCLKoutX_ADLY_MUX=1. If half step is enabled on either path, delay can be included by subtracting 0.5 from the enabled path. As an example, if DCLKoutX_DDLY_CNTH=7, DCLKoutX_DDLY_CNTL=6, SYSREF_DDLY=8, SDCLKoutY_DDLY=2 cycles, SYSREF_DIV=30, DCLKoutX_MUX=1, DCLKoutX_HS=0, SDCLKoutX_HS=0:
To calculate the expected time delay from the first edge of DCLKoutX to the first edge of SDCLKoutY, refer to Equation 3. Substitute the analog delays with the appropriate time values (in seconds) according to DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX and SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY. tsJESD204B is provided in the Electrical Characteristics section for the conditions in the example above as -80 ps.