SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
Sets the VCO1 VCO divider value. This divider cannot be bypassed, and has a minimum value of 2. This register is reserved for LMK04826 and LMK04828, and should be left unprogrammed.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7:5 | N/A | 0 | Reserved | |
4:0 | VCO1_DIV
(LMK04821 only) |
0 | When VCO_MUX selects VCO1 for LMK04821, the clock distribution frequency is equal to VCO1 frequency divided by this divide value. This divider is also on the PLL2 feedback path, and impacts the PLL2 N divider value.
Unlisted field values are reserved. |
|
Field Value | Divide Value | |||
0 (0x00) | 2 | |||
5 (0x05) | 3 | |||
10 (0x0A) | 8 | |||
20 (0x14) | 4 | |||
23 (0x17) | 5 | |||
27 (0x1B) | 7 | |||
30 (0x1E) | 6 |