SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
The LMK0482x family supports two types of zero-delay.
Cascaded zero-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux. The zero-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX. Because OSCin has a fixed deterministic phase relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode, the PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin); this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs.
Nested zero-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock (CLKinX) to the phase of a clock selected by the feedback mux. The zero-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX.
Without using zero-delay mode, there are numerous possible fixed phase relationships from clock input to clock output, depending on the clock output divide value. Careful selection of the zero-delay feedback value can reduce the number of fixed phase relationships from clock input to clock output, potentially to as few as one. As a result, zero-delay simplifies input-to-output phase guarantees, especially across multiple devices. For more information, see the application note Multi-Clock Synchronization.
Using an external zero-delay feedback prevents the use of CLKin1 for other purposes.