SNAS859 March   2024 LMK05318B-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Device Start-Up Modes
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 5.5 Thermal Information: 10-Layer Custom PCB
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL Mode
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO_P/N)
      2. 7.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With 1-PPS Inputs
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Amplitude Monitor
          3. 7.3.7.2.3 Frequency Monitoring
          4. 7.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 7.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 7.3.7.2.6 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 7.3.8.3.3 APLL2 Reference (R) Dividers
        4. 7.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.8.5  APLL Feedback Divider Paths
          1. 7.3.8.5.1 APLL1 N Divider With SDM
          2. 7.3.8.5.2 APLL2 N Divider With SDM
        6. 7.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 7.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 7.3.8.7.1 VCO Calibration
        8. 7.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 7.3.8.9  DPLL Reference (R) Divider Paths
        10. 7.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 7.3.8.11 DPLL Loop Filter (DLF)
        12. 7.3.8.12 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Channel Muxes
      11. 7.3.11 Output Dividers (OD)
      12. 7.3.12 Clock Outputs (OUTx_P/N)
        1. 7.3.12.1 AC-Differential Output (AC-DIFF)
        2. 7.3.12.2 HCSL Output
        3. 7.3.12.3 1.8V LVCMOS Output
        4. 7.3.12.4 Output Auto-Mute During LOL
      13. 7.3.13 Glitchless Output Clock Start-Up
      14. 7.3.14 Clock Output Interfacing and Termination
      15. 7.3.15 Output Synchronization (SYNC)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up Modes
        1. 7.4.1.1 EEPROM Mode
      2. 7.4.2 PLL Operating Modes
        1. 7.4.2.1 Free-Run Mode
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 Locked Mode
        4. 7.4.2.4 Holdover Mode
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 7.4.4.1 DCO Frequency Step Size
        2. 7.4.4.2 DCO Direct-Write Mode
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Communication
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Communication
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map and EEPROM Map Generation
      5. 7.5.5 General Register Programming Sequence
      6. 7.5.6 EEPROM Programming Flow
        1. 7.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 7.5.6.1.1 Write SRAM Using Register Commit
          2. 7.5.6.1.2 Program EEPROM
        2. 7.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 7.5.6.2.1 Write SRAM Using Direct Writes
          2. 7.5.6.2.2 User-Programmable Fields In EEPROM
      7. 7.5.7 Read SRAM
      8. 7.5.8 Read EEPROM
      9. 7.5.9 EEPROM Start-Up Mode Default Configuration
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PDN) Pin
      3. 8.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.3.1 Mixing Supplies
        2. 8.1.3.2 Power-On Reset (POR) Circuit
        3. 8.1.3.3 Powering Up From a Single-Supply Rail
        4. 8.1.3.4 Power Up From Split-Supply Rails
        5. 8.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 8.1.4 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
      2. 8.4.2 Device Current and Power Consumption
        1. 8.4.2.1 Current Consumption Calculations
        2. 8.4.2.2 Power Consumption Calculations
        3. 8.4.2.3 Example
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
        1. 8.5.3.1 Support for PCB Temperature up to 105°C
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

In a typical application, TI recommends the following steps:

  1. Use the LMK05318B-Q1 GUI in the TICS Pro programming software for a step-by-step design flow to enter the design parameters, calculate the frequency plan for each PLL domain, and generate the register settings for the desired configuration. The register settings can be exported (in hex format) to enable host programming or factory pre-programming.
    • If using a generic (non-custom) device, a host device can program the register settings through the serial interface after power up and issue a soft-reset (by RESET_SW bit) to start the device. The host can also store the settings to the EEPROM to allow automatic start-up with these register settings on subsequent power-on reset cycles.
  2. Tie the HW_SW_CTRL pin to ground to select EEPROM+I2C mode, or bias the pin to VIM through the weak internal resistors or external resistors to select EEPROM+SPI mode. Determine the logic I/O pin assignments for control and status functions. See Device Start-Up Modes for more information.
    • Connect I2C/SPI and logic I/O pins (1.8V compatible levels) to the host device pins with the proper I/O direction and voltage levels.
  3. Select an XO frequency by following Oscillator Input (XO_P/N) for more information.
    • Choose an XO with target phase jitter performance that meets the frequency stability and accuracy requirements required for the output clocks during free-run or holdover.
    • For a 3.3V LVCMOS driver, follow the OSC clock interface example in Figure 8-4. Power the OSC from a low-noise LDO regulator or optimize the power filtering to avoid supply noise-induced jitter on the XO clock.
    • TICS Pro: Configure the XO input buffer mode to match the XO driver interface requirements. See Table 7-1 for more information.
  4. Wire the clock I/O for each PLL domain in the schematic and use TICS Pro to configure the device settings as follows:
    • Reference inputs: Follow the LVCMOS or differential clock input interface examples in Figure 8-4 or in Clock Input Interfacing and Termination.
      • TICS Pro: For DPLL mode, configure the reference input buffer modes to match the reference clock driver interface requirements. See Table 7-2 for more information.
      • Use the LVCMOS clock input for input frequencies below 5MHz when amplitude monitoring is enabled.
    • TICS Pro: For DPLL mode, configure the DPLL input selection modes and input priorities. See Reference Input Mux Selection for more information.
    • TICS Pro: If APLL2 is used, configure the APLL2 reference for VCO1 domain (Cascaded APLL2) or XO clock (Non-cascaded APLL2).
    • TICS Pro: Configure each output with the required clock frequency and PLL domain. TICS Pro can calculate the VCO frequencies and divider settings for the PLL and outputs. Consider the following output clock assignment guidelines to minimize crosstalk and spurs:
      • OUT[0:3] bank is preferred for PLL1 clocks.
      • OUT[4:7] bank is preferred for PLL2 clocks.
      • Group identical output frequencies (or harmonic frequencies) on adjacent channelsand use the output pairs with a single divider (OUT0/1 or OUT2/3) when possible to minimize power.
      • Separate clock outputs when the difference of the two frequencies, |fOUTx – fOUTy|, falls within the jitter integration bandwidth (12kHz to 20MHz, for example). Any outputs that are potential aggressors must be separated by at least four static pins (power pin, logic pin, or disabled output pins) to minimize potential coupling. If possible, separate these clocks by the placing them on opposite output banks, which are on opposite sides of the chip for best isolation.
      • Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output clocks. If an LVCMOS output is required, use dual complementary LVCMOS mode (+/– or –/+) with the unused LVCMOS output left floating with no trace.
      • If not all outputs pairs are used in the application, consider connecting an unused output to a pair of RF coaxial test structures for testing purposes (such as SMA, SMP ports).
    • TICS Pro: Configure the output drivers.
      • Configure the output driver modes to match the receiver clock input interface requirements. See Table 7-6 for more information.
      • Configure any output SYNC groups that need the output phases synchronized. See Output Synchronization (SYNC) for more information.
      • Configure the output auto-mute modes, output mute levels, and APLL and DPLL mute options. See Output Auto-Mute During LOL for more information.
    • Clock output Interfacing: Follow the single-ended or differential clock output interface examples in Figure 8-4 or in Clock Output Interfacing and Termination.
      • Differential outputs must be AC-coupled and terminated and biased at the receiver inputs.
      • HCSL outputs must have 50Ω termination to GND (at source or load side) unless the internal source termination is enabled by programming.
      • LVCMOS outputs have internal source termination to drive 50Ω traces directly. LVCMOS VOH level is determined by VDDO voltage (1.8V).
    • TICS Pro: Configure the DPLL loop bandwidth.
      • Below the loop bandwidth, the reference noise is added to the TDC noise floor and the XO/TCXO/OCXO noise. Above the loop bandwidth, the reference noise is attenuated with roll-off up to 60dB/decade. The optimal bandwidth depends on the relative phase noise between the reference input and the XO. The loop bandwidth of the APLL1 can be configured to provide additional attenuation of the reference input, TDC, and XO phase noise above the bandwidth of the APLL1 (typically around 1kHz).
    • TICS Pro: Configure the maximum TDC frequency to optimize the DPLL TDC noise contribution for the desired use case.
      • Wired: The maximum TDC rate is preset to 400kHz. This supports SyncE and other use cases using a narrow loop bandwidth (≤10Hz) with a TCXO/OCXO/XO to set the frequency stability and wander performance.
      • Wireless: The maximum TDC rate is preset to 26MHz for lowest in-band TDC noise contribution. This supports wireless and other use cases where close-in phase noise is critical.
      • Custom: The maximum TDC rate can be specified for any value up to 26MHz.
    • TICS Pro: If clock steering is needed (such as for IEEE 1588 PTP), enable DCO mode for the DPLL loop and enter the frequency step size (in ppb). The FDEV step register is computed according to DCO Frequency Step Size. Enable the FINC/FDEC pin control on the GPIO pins, if needed.
  5. TICS Pro: Configure the reference input monitoring options for each reference input. Disable the monitor when not required or when the input operates beyond the supported frequency range of the monitor. See Reference Input Monitoring for more information.
    • Amplitude monitor: Set the LVCMOS detected slew rate edge or the differential input amplitude threshold to monitor input signal quality. Disable the monitor for a differential input below 5MHz or else use an LVCMOS input clock.
    • Missing pulse monitor: Set the late window threshold (TLATE) to allow for the longest expected input clock period, including worst-case cycle-to-cycle jitter. For a gapped clock input, set TLATE based on the number of allowable missing clock pulses.
    • Runt pulse monitor: Set the early window threshold (TEARLY) to allow for the shortest expected input clock period, including worst-case cycle-to-cycle jitter.
    • 1-PPS Phase validation monitor: Set the phase validation jitter threshold, including worst-case input cycle-to-cycle jitter.
    • Validation timer: Set the amount of time the reference input must be qualified by all enabled input monitors before the input is valid for selection.
  6. TICS Pro: Configure the DPLL lock detect and tuning word history monitoring options for each channel. See PLL Lock Detectors and Tuning Word HistoryTuning Word History for more information.
    • DPLL tuning word history: Set the history count/averaging time (TAVG), history delay/ignore time (TIGN), and intermediate averaging option.
    • DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.
  7. TICS Pro: Configure each status output pin and interrupt flag as needed. See Status Outputs and Interrupt for more information.
    • Select the desired status signal selection, status polarity, and driver mode (3.3V LVCMOS or open-drain). Open-drain requires an external pullup resistor.
    • If the Interrupt is enabled and selected as a status output, configure the flag polarity and the mask bits for any interrupt source, and the combinational AND/ OR gate as needed.
  8. Consider the following guidelines for designing the power supply:
    • Outputs with identical frequency or integer-related (harmonic) frequencies can share a common filtered power supply.
      • Example: 156.25MHz and 312.5MHz outputs on OUT[0:1] and OUT[2:3] can share a filtered VDDO supply (Group 1), while 100MHz, 50MHz, and 25MHz outputs on OUT[4:7] can share a separate VDDO supply (Group 2).
    • For lowest power, AC-DIFF or HCSL outputs can be powered from a 1.8V supply with no degradation in output swing or phase noise (compared to 2.5V or 3.3V).
    • 1.8V LVCMOS outputs must be powered from a 1.8V supply.
    • See Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains.