SNAS815B december   2020  – june 2023 LMK1D1204 , LMK1D1208

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input and Hysteresis
      2. 9.3.2 Input Mux
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

GUID-32CA2E5A-9C9F-40B4-810D-AAC5A109DCBB-low.gifFigure 8-1 LVDS Output DC Configuration During Device Test
GUID-20210806-CA0I-CW0H-6LBR-F02QSQV71C5V-low.svg Figure 8-2 LVDS Output AC Configuration During Device Test
GUID-E65C43A9-384E-4D1C-A4B5-D07686BA9BB0-low.gifFigure 8-3 DC-Coupled LVCMOS Input During Device Test
GUID-849A7031-D9C6-45E8-9C14-0EBA89FED56E-low.gifFigure 8-4 Output Voltage and Rise/Fall Time
GUID-FD632F74-AB65-414C-8721-BCF8356FF54B-low.gif
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 8-5 Output Skew and Part-to-Part Skew
GUID-AEFF5132-73D3-4D91-9297-89FE8FB36CEF-low.gifFigure 8-6 Output Overshoot and Undershoot
GUID-CFE6DDF1-B162-4E50-9C8E-AD16FDEC21DF-low.gifFigure 8-7 Output AC Common Mode