SNAS880 December 2024 LMK3C0105
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
R10 is shown in Table 8-16.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Reserved | R/W | 0x0 | Reserved. Only write '0' to this bit. |
14:11 | PROD_REVID | R | N/A | Product revision identifier. |
10 | CLK_READY | R | N/A | CLK_READY status. The REF_CTRL pin mirrors this status signal when the pin functions as a "clock ready" signal. |
9 | Reserved | R | N/A | Reserved, do not write to this field. |
8 | RB_PIN_15 | R | N/A | Readback of the REF_CTRL pin. |
7 | RB_PIN_4 | R | N/A | Readback of the OTP_SEL1/SDA pin. |
6 | RB_PIN_3 | R | N/A | Readback of the OTP_SEL0/SCL pin. |
5 | RB_PIN_2 | R | N/A | Readback of the I2C_ADDR pin. |
4 | DEV_IDLE_STATE_SEL | R/W | 0x1 | This bit controls the behavior of the device when both outputs are disabled. Placing the device into a low-power state is not recommended for PCIe applications, as the time to re-enable the clocks is extended. This field is stored in the EFUSE. 0h: When both outputs are disabled, the outputs are muted, and the device is placed into a low-power state. 1h: When both outputs are disabled, the outputs are muted. The device does not enter a low-power state. |
3 | PIN_RESAMPLE_DIS | R/W | 0x0 | This bit controls the resampling of the device pins when exiting the low power mode. Write this bit while in the low power mode. TI recommends keeping this bit as a '1' unless the functionality is explicitly desired. 0h: Pin resampling is enabled. When exiting the low power mode, the I2C_ADDR, OTP_SEL0/SCL, OTP_SEL1/SDA, and I2C_ADDR pins are resampled. If I2C_ADDR is high, the device enters OTP Mode. 1h: Pin resampling is disabled. When exiting the low power mode, the I2C_ADDR, OTP_SEL0/SCL, OTP_SEL1/SDA, and I2C_ADDR pins are not resampled. The device remains in I2C Mode. |
2 | OTP_AUTOLOAD_DIS | R/W | 0x0 | This bit controls the behavior of the device when exiting the low power mode. Write this bit while in the low power mode. TI recommends keeping this bit as a '1' unless the functionality is explicitly desired. 0h: OTP autoload is enabled. When exiting the low power mode, the contents of OTP Page 0 are written to the device registers. 1h: OTP autoload is disabled. When exiting the low power mode, the contents of OTP Page 0 are not written to the device registers. |
1 | PDN | R/W | 0x0 | Writing a '1' to this bit puts the device into a low power state. |
0 | Reserved | R/W | 0x0 | Reserved. Only write '0' to this bit. |