SNAS880 December   2024 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

Device Configuration Control

Figure 7-2 shows the relationships between device states, the configuration pins, device initialization, and device operational modes. OTP mode is entered when the REF_CTRL pin is pulled high at start-up. I2C mode is entered when the REF_CTRL pin is pulled low at start-up. In OTP mode, the state of the OTP_SEL0/SCL and OTP_SEL1/SDA pins determines the OTP page that is loaded into the active registers. The device is one-time programmable, meaning that the register settings stored into the internal EFUSE can not be changed. The device can be transitioned from OTP to I2C mode, or reciprocally, by changing the state of the REF_CTRL pin, then triggering a device power cycle by pulling VDD low, then high again. In OTP mode, a change in the level of the OTP_SEL0 or OTP_SEL1 pins, followed by pulling the REF_CTRL pin high dynamically changes the active OTP page. The time between the first OTP_SEL pin change and pulling REF_CTRL high must be less than 350 us, otherwise the device enters I2C Mode.

In I2C mode, the state of the I2C_ADDR pin can determine the I2C address of the device, with the OTP_SEL0/SCL and OTP_SEL1/SDA pins re-purposed as I2C clock and data pins, respectively. In I2C mode, the host can update the active device registers. If using a configuration different than the programmed configuration, the registers must be written after each power cycle.

The device can be placed into a low power state by setting the PDN bit (R10[1]) to '1'. Clearing the PDN bit takes the device out of the low power state. If DEV_IDLE_STATE_SEL bit (R10[4]) is a '0' and the outputs are disabled, the device enters the low power state. Entering the low power state is required for changing the frequency of the FOD used by Channel 0, changing the SSC configuration, and changing the output format. TI recommends performing register writes within this low power state. Set the OTP_AUTOLOAD_DIS (R10[2]) bit to a '1' to prevent automatic loading of OTP Page 0 prior to setting PDN to '0'.

There are two fields that determine the state of the device when coming out of the low power state. PIN_RESAMPLE_DIS (R10[3]) controls whether or not the I2C_ADDR, OTP_SEL0/SCL, OTP_SEL1/SDA, and REF_CTRL pins are resampled when exiting the low power state. If the pins are resampled, the device can be transitioned into OTP mode if the REF_CTRL pin is pulled high. Set this bit to a '1' to disable this functionality. OTP_AUTOLOAD_DIS controls whether or not the contents of OTP Page 0 are loaded into the device registers when exiting the low power state. If OTP_AUTOLOAD_DIS bit is a '1' and PIN_RESAMPLE_DIS is a '1', then the register contents do not change. If OTP_AUTOLOAD_DIS bit is a '0' and PIN_RESAMPLE_DIS is a '1', then the contents of OTP Page 0 are loaded to the registers. If PIN_RESAMPLE_DIS is a '0' and REF_CTRL is pulled high, then the device enters OTP Mode. In this case, OTP_SEL0/SCL and OTP_SEL1/SDA control the OTP page loaded into the device registers.

LMK3C0105 LMK3C0105 Device Mode Diagram Figure 7-2 LMK3C0105 Device Mode Diagram

In I2C Mode, the device registers are from the contents of OTP Page 0. In OTP mode, these values come from one of the four OTP pages, selectable based on the state of the OTP_SELx pins on start-up. Figure 7-3 shows interface and control blocks within the LMK3C0105, with the arrows referring to read and write access from the different embedded memories.

LMK3C0105 LMK3C0105 Interface and Control BlocksFigure 7-3 LMK3C0105 Interface and Control Blocks