SNAS880 December   2024 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

8.1.8 R7 Register (Address = 0x7) [reset = 0x5D1F]

R7 is shown in Table 8-16.

Return to the Summary Table.

Table 8-10 R7 Register Field Descriptions
Bit Field Type Reset Description
15 Reserved N/A 0x0 Reserved, do not write to this field.
14:13 REF_CTRL_PIN_FUNC R/W 0x2

Sets the function of the REF_CTRL pin. This field is stored in the EFUSE.

0h: REF_CTRL pin disabled, pulled to GND.

1h: REF_CTRL pin disabled, tri-state.

2h: REF_CTRL pin functions as an additional LVCMOS REF_CLK output.

3h: REF_CTRL pin functions as "clock ready" signal.
12:11 REF_CLK_DIV R/W 0x3

REF_CLK output divisor value when REF_CTRL is used as REF_CLK. This field is stored in the EFUSE.

0h: REF_CLK disabled.

1h: FOD / 2.

2h: FOD / 4.

3h: FOD / 8.
10 Reserved R/W 0x1 Reserved. Do not write any value other than '1' to this field.
9 REF_CLK_FOD_SEL R/W 0x0

Select the FOD used to generate the REF_CLK output. This field is stored in the EFUSE.

0h: FOD0.

1h: FOD1.
8 OUTCD_EN R/W 0x1

Output Enable bit for OUTC and OUTD. This field is stored in the EFUSE.

0h: OUTC and OUTD are disabled.

1h: OUTC and OUTD are enabled.
7 OUTCD_CH_SEL R/W 0x0

Selects the source for OUTC/OUTD. This field is stored in the EFUSE.

0h: OUTC and OUTD are sourced from Channel Divider 0.

1h: OUTC and OUTD are sourced from Channel Divider 1.
6:5 Reserved R/W 0x0

Reserved, only write '0' to this field.
4:2 OUTCD_FMT R/W 0x7

Selects the output format for OUTC and OUTD. This field is stored in the EFUSE.

0h: Reserved.

1h: Reserved.

2h: Reserved.

3h: Reserved.

4h: LVCMOS, OUTC enabled, OUTD disabled.

5h: LVCMOS, OUTC disabled, OUTD enabled.

6h: LVCMOS, OUTC enabled, OUTD enabled, 180 degrees out of phase.

7h: LVCMOS, OUTC enabled, OUTD enabled, OUTC and OUTD in phase.
1 OUTAB_EN R/W 0x1

Output Enable bit for OUTA and OUTB. This field is stored in the EFUSE.

0h: OUTA and OUTB are disabled.

1h: OUTA and OUTB are enabled.
0 OE_PIN_POLARITY R/W 0x1

OE pin polarity selection. This bit does not affect the polarity of the OUTx_EN bits, only the OE pin. This field is stored in the EFUSE.

0h: OE is active high (OE tied to VDD enables outputs).

1h: OE is active low (OE tied to GND enables outputs).